11-14-2018 03:34 AM - edited 11-14-2018 03:35 AM
I'm trying to run SHA256 on aws f1 instance using opencl. The target clock for opencl kernel is 250 MHz, but during implementation process it was slowed down: "WARNING: One or more timing paths failed timing targeting 250 MHz for kernel clock 'DATA_CLK'. The frequency is being automatically changed to 81.6 MHz to enable proper functionality".
I haven't found something useful in system estimate and csynth report. The estimated frequency for kernel was almost ~1.5 times bigger, than target.
Opening design implementation in vivado shows, that slack for kernel clock is very big:
Below is clock critical path:
The critical path begins on the synchronous flip-flop:
And after passing tons of asynchronous elements it ends on synchronous flip-flop:
1. Does the SDAccel framework has tools which could help us to find which instruction in opencl code results in bunch of async logic?
2. If no, how can we modify result HDL code, currently it's very unclear and contains 26k lines of code.
11-14-2018 11:40 PM
It's recommended to open Vivado HLS from SDAccel.
In Vivado HLS project, click "export RTL" button. In prompting window, check "Vivado synthsis,place and route". Click ok. This way, HLS will call Vivado to do Synthesis and Routing only for the kernel, excluding SDAccel platform logics. Pay attention to the last timing result of Vivado Synthesis and Route.
Then, you may see if this issue mainly comes from HLS. If above steps show similar timing failure, you may focus on timing optimization on HLS.
11-15-2018 11:18 PM
After building the design in Hw-Emulation, you can click the hls launching button in "Hardware Function" window by selecting the target function.
Then export RTL in HLS project.
11-16-2018 06:09 AM
I've opened example project in HLS using SDx.
How can I observe, that some statements in my kernel code lead to long chains of async logic?
Can synthesized project be opened in Vivado to open schematic?