02-05-2019 09:04 AM
I'm trying to follow the rtl workflow in order to integrate a custom rtl kernel.
I'm using an alveo u200 and vivado/sdaccel 2018.3
I'm creating an IP using hls, then import into vivado and export it as an IP.
Here I use the "export current project" option in the wizard.
As long as I know, I set the address map for the axi mater (m_axi_gmem) to be the full 64b range starting from 0.
s_axi_control is mapped as 64k slave starting from 0.
Then I package it as a .xo file.
Find attached the xml description file as well as the resulting xo file.
Finally, xocc finish with an error after some time:
ERROR: [XOCC 60-399] xclbinutil failed, please see log file for detail: '/home/afilguer/vadd_hls_test/hls/ipintegrator/_x/link/int/bin_vadd_hw_xclbinutil.log' ERROR: [XOCC 60-626] Kernel link failed to complete ERROR: [XOCC 60-703] Failed to finish linking
Looking at the suggested log, some lines look suspicious:
WARNING: Skipping IP_LAYOUT section for count size is zero. WARNING: Section 'IP_LAYOUT' content is empty. No data in the given JSON file. WARNING: Skipping CONNECTIVITY section for count size is zero. WARNING: Section 'CONNECTIVITY' content is empty. No data in the given JSON file
I found that ip_layout and connectivity are empty in bin_vadd_hw.rtd
From the vadd opencl example in SDAccel, it looks like these should not be empty. However I don't know what's going on.
Find attached the vivado project, exported IP and hls files that generate the IP for the vivado project, as well as some more log files I think can be useful.
02-11-2019 06:35 PM
Do you encounter the same issue with the example design in your environment?
02-12-2019 01:27 AM
I managed to build and run the example vadd application without any issue.
I also managed to build an xclbin directly from an hls IP, but as soon as I place it in a block design and export as an IP, I get these messages.