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SDAccel 2016.4 Memory bank error

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Visitor
Posts: 10
Registered: ‎05-17-2017

SDAccel 2016.4 Memory bank error

Hi,

I'm trying to use multiple memory banks to improve memory access efficience. I followed these instructions:

1. Assigning DDR Bank in Host Code

2. Assigning DDR Bank in Kernel Code

 

but I got this error:

ERROR: Memory bank specified for kernel instance "krnl_vadd_1" of kernel "krnl_vadd" for argument index 1 does not match the physical connectivity from the binary.
Bank specified on host side is "M01_AXI" while bank from the binary is "M00_AXI".

 

I'm using SDAccel 2016.4 and the kernel is written in OpenCL C.

 

I also tried to modify the makefile by appending pamameters below,

xocc --max_memory_ports krnl_vadd 
--xp misc:map_connect=add.kernel.krnl_vadd_1.M_AXI_GMEM0.core.OCL_REGION_0.M00_AXI 
--xp misc:map_connect=add.kernel.krnl_vadd_1.M_AXI_GMEM1.core.OCL_REGION_0.M01_AXI

 and run `make all` in termimal. But the error is still there when I run `./host.exe xxx.xclbin`.

 

How can I fix this error?

Xilinx Employee
Posts: 6
Registered: ‎01-12-2017

Re: SDAccel 2016.4 Memory bank error

[ Edited ]

Hi @ezalor927

 

Please have a look at this Xilinx SDAccel Github example

Github Multiple Memory Banks - OpenCL (C/C++) Kernel 

 

Thanks

Kali

Visitor
Posts: 13
Registered: ‎05-19-2017

Re: SDAccel 2016.4 Memory bank error

At the risk of pointing out the obvious, the bank assignment in the host code needs to match the Makefile. Can you share the portion of the host code that does the bank assignment? 

Visitor
Posts: 10
Registered: ‎05-17-2017

Re: SDAccel 2016.4 Memory bank error

Hi, @ywu1,

Here is my host code (PS: cpp file cannot be uploaded, So I changed the file extension)and makefile.

It just looks like the gmem_2banks_ocl example, but it doesn't work.

 

Thank you!

 

Visitor
Posts: 13
Registered: ‎05-19-2017

Re: SDAccel 2016.4 Memory bank error

I suggest you make clean and double check that all binaries and intermediate objects files are removed. Then re-run.