We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎04-03-2018

SDAccel FPGA utilization Estimate


From UG1164 SDAccel platform will contain several IPs (in the static and dynamic regions) and also the kernel. However, After synthesizing  kernel code in both SDAccel and HLS, the resource estimated by SDAccel in the HW emulation report or system report is very close to HLS.


1- Is utilization estimated in the SDAccel includes static region and DDR IPs? E.g. 80% of LUTs and BRAMs are utilized by my kernel. Is IP resources included in this estimation? or I should free up some resources for these IPs?


2- If utilization estimated NOT includes IPs, why the estimate in the HLS and SDAccel not exactly matches to each other (have small differences)?


0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎09-08-2011

Re: SDAccel FPGA utilization Estimate

Hi yyyyaaaayyyy4,


    It depends what you are looking at.. But you should see something like:




Which shows you the User Budget, the Kernel, and the platform.


This should give you an idea of the Budget. The HLS is just the kernel results from the HLS sub project. Both of these are estimates as well unless you are looking at the final implemented results.


So you might see differences depending where you look, and the fact that they are Utilization Estimates from the tools.







If at first you don't succeed, try redefining success?
0 Kudos