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Observer calibra
Observer
446 Views
Registered: ‎06-20-2012

SDAccel fail with only vector ports

The following error appear:

Loading: '../binary_container_1.xclbin'

ERROR: Missing AXI Slave (control) port for kernel krnl_vadd

ERROR: program is nullptr

When I compile this simple code.

 

extern "C" {

void krnl_vadd( const int* a, const int* b, nt* c)

{

#pragma HLS INTERFACE m_axi depth=512 port=a offset=slave bundle=gmem

#pragma HLS INTERFACE m_axi depth=512 port=b offset=slave bundle=gmem

#pragma HLS INTERFACE m_axi depth=512 port=c offset=slave bundle=gmem

#pragma HLS INTERFACE s_axilite port=return bundle=control

int arrayA[10];

readA: for (int j = 0 ; j < 10 ; j++) arrayA[j] = a[j];

vadd_wrteC: for (int j = 0 ; j < 10 ; j++) c[j] = arrayA[j] + b[j];

}

}

 

A dummy port solves the problem:

extern "C" {

void krnl_vadd( const int* a,const int* b, int* c, const int dummy)

{

#pragma HLS INTERFACE m_axi depth=512 port=a offset=slave bundle=gmem

#pragma HLS INTERFACE m_axi depth=512 port=b offset=slave bundle=gmem

#pragma HLS INTERFACE m_axi depth=512 port=c offset=slave bundle=gmem

#pragma HLS INTERFACE s_axilite port=return bundle=control

#pragma HLS INTERFACE s_axilite port=dummy bundle=control

 

    int arrayA[10];

readA: for (int j = 0 ; j < 10 ; j++) arrayA[j] = a[j];

vadd_wrteC: for (int j = 0 ; j < 10 ; j++)

c[j] = arrayA[j] + b[j];

}

}

Loading: '../binary_container_1.xclbin'

TEST PASSED

 

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1 Reply
Xilinx Employee
Xilinx Employee
377 Views
Registered: ‎06-08-2018

Re: SDAccel fail with only vector ports

Hi,

 

As for I know, it's because of axi implementation.

When a kernel starts the AXI transaction (read/write from/to memory), some basic information (i.e. address) is required.

So, your kernel needs to have a axi-lite port (like your dummy port) to get those information from the host.

 

I hope this can answer your question.

 

Regards,

Haeseung