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Streaming signals

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Posts: 27
Registered: ‎09-30-2016
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Streaming signals

Hello all,

 

I was going through the Vision examples in the GitHub repo, and the examples read from a *.bmp files for processing. 

What would be the best way to stream a real time signal (video or just digital signals) in SDAccel? 

 

Thanks!

 


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Moderator
Posts: 8,649
Registered: ‎02-27-2008

Re: Streaming signals

Might I suggest ....

 

That you stay in c, c++?  In the reVision Base TRD, you develop the entire flow in c/c++.  You test it in c.  If it isn't fast enough, you selectively target c to be turned into programmable logic (placed in the PL).  All this happens 'under the hood' using Vivado HLx.  If that STILL isn't fast enough, you may export the hardware (dsa file) roll up you sleeves, and descend into verilog or VHDL to gain the performance you need by going massively parallel in a custom block to do what is needed.

 

https://forums.xilinx.com/t5/Xcell-Daily-Blog/Megvii-s-Face-facial-recognition-algorithm-has-drawn-300K/ba-p/804737

 

Is just one example of what is possible.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Moderator
Posts: 8,649
Registered: ‎02-27-2008

Re: Streaming signals

Have you looked at the reVision Base TRD 2017.2?

 

http://www.wiki.xilinx.com/reVISION+Getting+Started+Guide+2017.2

 

Supports HDMI in, USB in, or MIPI in.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Observer
Posts: 27
Registered: ‎09-30-2016

Re: Streaming signals

Thank you Austin. This is a great resource for me to get on the embedded solution and certainly where I am headed for the end product. For developmet, using SDAccel, I am reading off files from the host, and transferring it to the device. 

 

I am trying to see if there is a better way to stream signals (or data) besides using OpenCL API such as usingclEnqueueReadBuffer/usingclEnqueueWriteBuffer that is in basic example such as 

https://github.com/Xilinx/SDAccel_Examples/blob/master/getting_started/host/data_transfer_ocl/src/host.cpp

 

 

Moderator
Posts: 8,649
Registered: ‎02-27-2008

Re: Streaming signals

Might I suggest ....

 

That you stay in c, c++?  In the reVision Base TRD, you develop the entire flow in c/c++.  You test it in c.  If it isn't fast enough, you selectively target c to be turned into programmable logic (placed in the PL).  All this happens 'under the hood' using Vivado HLx.  If that STILL isn't fast enough, you may export the hardware (dsa file) roll up you sleeves, and descend into verilog or VHDL to gain the performance you need by going massively parallel in a custom block to do what is needed.

 

https://forums.xilinx.com/t5/Xcell-Daily-Blog/Megvii-s-Face-facial-recognition-algorithm-has-drawn-300K/ba-p/804737

 

Is just one example of what is possible.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Observer
Posts: 27
Registered: ‎09-30-2016

Re: Streaming signals

Awesome example. I think I will do just that for the sake of optimization. I like rolling up the sleeves and getting all "greasy"!