UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
753 Views
Registered: ‎01-27-2018

XOCC options for AXI configuration

Hi,

I am trying to implement a custom RTL kernel with SDAccel. I am currently using the AXI Master provided by the example produced by the Xilinx RTL Kernel Wizard. 

I would like to set the memory port width at 32 bits instead of 512. I am trying to do that with the options provided to the XOCC command:

 

xocc ... --max_memory_ports all --memory_port_data_width all:32

 

Even giving these options when I launch the hw_emulation the AXI master produces bursts transactions with 512 bits wide beats instead of 32.

 

Where should I intervene in order to correctly change the port data width configuration?

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
718 Views
Registered: ‎09-08-2011

Re: XOCC options for AXI configuration

Hi Alessandro.comodi, How do you have your top level ports setup? Can you share your Kernel details? Can you change it from all:32 to the actual kernel name? It might give more messages if it fails Can you look at the log as well and share the messages related to the xocc flags? Thanks, Evan
If at first you don't succeed, try redefining success?
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
497 Views
Registered: ‎06-20-2018

Re: XOCC options for AXI configuration

@alessandro.comodi, go to Xilinx RTL Kernel Wizard "Global Memory" window, change Width from "64" (bytes, default) to "4" (bytes), then, the AXI master memory port has the data width "32" bits (=4 bytes). 

0 Kudos