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Visitor suming
Visitor
463 Views
Registered: ‎03-13-2019

how to use both multiple ddr bank and multiple compute unit in SDAccel?

there are examples about using multi ddr bank and multi compute unit separately in SDAccel. but how to use both. for example, in a project, i have two compute units, and compute unit 1 connect to ddr bank0, compute unit 2 connect to ddr bank1. does the SDAccel support?
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6 Replies
Xilinx Employee
Xilinx Employee
443 Views
Registered: ‎07-16-2008

回复: how to use both multiple ddr bank and multiple compute unit in SDAccel?

Yes, you can specify kernel instance name in --sp option of xocc.

--sp <COMPUTE_UNIT>.<MEM_INTERFACE>:<MEMORY>

Refer to specific version of SDAccel User Guide for syntax example.

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Xilinx Employee
Xilinx Employee
429 Views
Registered: ‎06-04-2018

回复: how to use both multiple ddr bank and multiple compute unit in SDAccel?

Hi @suming,

You can check xilinx LZ4 Compression for reference.

https://github.com/Xilinx/Applications/blob/master/data_compression/xil_lz4/Makefile

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Visitor suming
Visitor
297 Views
Registered: ‎03-13-2019

回复: how to use both multiple ddr bank and multiple compute unit in SDAccel?

Hi @bchebrol 
Thanks for your reply. this is the example i want to find.
But i have other question.
Every CU is identified in xil_lz4/src/xil_lz4.cpp.
for (int i = 0; i < C_COMPUTE_UNIT; i++)
compress_kernel_lz4[i] = new cl::Kernel(*m_program, compress_kernel_names[i].c_str());
And compress_kernel_names is defined in xil_lz4/src/xil_lz4.h.
std::vector<std::string> compress_kernel_names = {"xil_lz4_cu1",
"xil_lz4_cu2",
"xil_lz4_cu3",
"xil_lz4_cu4",
"xil_lz4_cu5",
"xil_lz4_cu6",
"xil_lz4_cu7",
"xil_lz4_cu8",
};
when i use this method, there is error that can not find the xxx_cu1. why it got this error? i already set the CU number to 2. does there need other settings?

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Visitor suming
Visitor
297 Views
Registered: ‎03-13-2019

回复: how to use both multiple ddr bank and multiple compute unit in SDAccel?

Hi @bchebrol 
Thanks for your reply. this is the example i want to find.
But i have other question.
Every CU is identified in xil_lz4/src/xil_lz4.cpp.
for (int i = 0; i < C_COMPUTE_UNIT; i++)
compress_kernel_lz4[i] = new cl::Kernel(*m_program, compress_kernel_names[i].c_str());
And compress_kernel_names is defined in xil_lz4/src/xil_lz4.h.
std::vector<std::string> compress_kernel_names = {"xil_lz4_cu1",
"xil_lz4_cu2",
"xil_lz4_cu3",
"xil_lz4_cu4",
"xil_lz4_cu5",
"xil_lz4_cu6",
"xil_lz4_cu7",
"xil_lz4_cu8",
};


when i use this method, there is error that can not find the xxx_cu1. why it got this error? i already set the CU number to 2. does there need other settings?

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Xilinx Employee
Xilinx Employee
279 Views
Registered: ‎01-12-2017

回复: how to use both multiple ddr bank and multiple compute unit in SDAccel?

Hi @suming 

This error is observed when you made changes to your source or the xil_lz4 link provided by @bchebrol  ? 

By default we have set 2 CUs for computation. 

 

Thanks

Kali

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Xilinx Employee
Xilinx Employee
215 Views
Registered: ‎07-18-2014

回复: how to use both multiple ddr bank and multiple compute unit in SDAccel?

Hi @suming ,

Currently tere are some known issues of supporting multiple Compute units which are connected to different DDRs (non identical case).  

Below LZ4 example is not a multiple compute units example:

https://github.com/Xilinx/Applications/blob/master/data_compression/xil_lz4

Above example is providing a workaround to handle the case. It has different kernel names which has exact identical functionality but different ddr connection.

So in host code, individual kernel has to be called in host code with thier respective name.

 

-Heera

 

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