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Visitor canh.ld
Registered: ‎07-01-2018

implementation flow does not meet timing in SDAccel

When I compiled my design there's error : "design did not meet timing, auto frequency scaling failed because an unscalable system clock did not meet the target frequency. Please try specifying a clock frequency lower than 300 using the '--kernel_frequency' switch for the next compilation". I can work-around this error by reducing the kernel frequency to 150 MHz, however, it's also reduce the performance by half. I've tried to optimize my kernel and the estimated frequency in the system_estimate.xtxt is ~378 MHz, but finally I could only run my kernel at 150MHz, because of this error. So what I want to ask is how can I run my kernel at 378 MHz? And if I can't, how can I chose a "proper" kernel frequency value when I compile my kernel?

I'm using kcu1500 card, SDAccel 2017.1 

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Xilinx Employee
Xilinx Employee
Registered: ‎03-24-2010

Re: implementation flow does not meet timing in SDAccel

Something to check:

1. Make sure kernel itself can run above 300M. System estimation should be an estimation. Try to evaluate kernel with Vivado Synthesis and Vivado Implementation to see the performance.

2. Check kernel usage of resources. For each kernel, it should not occupy resources above one SLR. 

3. Check the timing failure path in Vivado to find any hint. Find the dcp file in a directory impl_1. When necessary, refer to UG949 for timing closure techniques.

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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