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Observer sbuschjaeger
Registered: ‎07-29-2015

Automatically generate HDL interface



The SDSoC user guide (ug1027) chapter 8 mentions, that it is possible to include packaged IP cores written in HDL languages into the project directly. However, I was wondering, if it is possible to automatically generate an HDL interface based on a *.c file, then implement the desired functionality in HDL myself (and test in in vivado etc) and later package the core and use it in SDSoC. 


Alternatively, I think vivado can already automatically generate AXI interfaces and package my IP core. Is it possible to use such an IP core within SDSoC? If so, are there any tutorials on this subject?

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Xilinx Employee
Xilinx Employee
Registered: ‎06-29-2015

Re: Automatically generate HDL interface

Hi sbuschjaeger,


Regarding " is possible to automatically generate an HDL interface based on a *.c file", I dont think anything like this exists. What interface are you hoping to get generated for free? You should be able to use any standard AXI interface for most of your needs (either AXI-LIte or AXI-Stream). AXI-Stream is pretty straight forward (almost like FIFO). AXI-Lite interfaces abound on the internet (something like googling for "axi lite interface verilog" should net you a couple examples). 


Regarding using IP's produced using the vivado generated axi-interfaces, you should be able to use the defined flow in the user guides to integrate with SDSoC. Take a look at the examples and post again if you have any questions.


Good Luck!

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