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kardec
Adventurer
Adventurer
558 Views
Registered: ‎01-30-2018

[CHaiDNN] concat modules disconnected in block design

Hi guys,

I've followed the "build from source" guide to create the hardware in Vivado.

 

This block design is the result:

 

cap_vivado.png

 

As you can see, both concat modules are disconnected. Their inputs are disconnected.

 

I guess this is an error, am I right?

How can I solve that?

 

Thanks in advance.

 

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tanders
Xilinx Employee
Xilinx Employee
535 Views
Registered: ‎03-31-2011

There's nothing in the Tcl that connects these input ports.  I'm not that familiar w/ this design yet, but these are likely used as inputs down the flow.  Continue on, as you can create the complete the rest of the design as it stands. 

 

I got the same block diagram working through this and was able to create the DSA

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