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lt23yuan_lm
Observer
Observer
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Registered: ‎07-11-2018

Can SDSoC invoke a c-callable IP that needs to read/write data in PL DDR?

Hello,

 

From my previous practice, the HLS IP can be packed with all the AXI interfaces visible for SDSoC applications.  However, right now I have a HLS IP, which needs to read data from the PL DDR, and then send the processed results to PS DDR. In this case, how should I pack this IP in HLS, and then use it in an SDSoC application?

 

Thanks for all possible help!

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lt23yuan_lm
Observer
Observer
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Registered: ‎07-11-2018

It seems that there are already some discussions about this topic before:

 

https://forums.xilinx.com/t5/SDSoC-Environment-and-reVISION/use-pl-ddr-in-sdsoc/m-p/815320/highlight/true#M1444

 

In my case, I think I need to:

1) add the MIG IP to PS as a AXI memory device in the platform description

2) use sds_mmap to associate the input/output arrays in the MIG space

3) invoke the accelerator function which accesses data in the specified arrays in MIG space

 

I need time to have a try. Anyone who can share his experiences about it is welcome.

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lt23yuan_lm
Observer
Observer
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Registered: ‎07-11-2018

I made some experiments. Right now, a HW toggled function can access data from the PL DDR memory. However, the data motion report shows that this function utilizes the s_axi port, which implies that data are moved from PL DDR to PS side before being fetched by the HW function. It will be more efficient if the function in PL can read data directly from PL DDR. Is there any solution?

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