UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor victor1969
Visitor
138 Views
Registered: ‎02-26-2016

HLS IP direct connection to a C-callable IP

I'm using a C-callable IP. It's a LDPC decoder previously design at RTL level and packaged with sdx_pack

This is the declaration:

#pragma SDS data access_pattern(y_rx:SEQUENTIAL,c_final:SEQUENTIAL)
void NMS_decoder_AXI_STREAM(int y_rx[128], int c_final[128]);

where y_rx is mapped to an AXI_STREAM input and c_final to an AXI_STREAM output

I call the NMS_decoder_AXI_STREAM function in my main code and SDSOC is making synthesis correctly. Checked on a ZCU102 board.

The y_rx input is generated from a c function. Now, I order the SDSOC tool to make that function in hardware. It uses HLS to make that task. The problem is that it is not making a direct HW connection between both HW modules. It is passing y_rx value through memory (via DMAs).

How can I force a direct connection?

0 Kudos