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Visitor radhikamkr
Visitor
355 Views
Registered: ‎07-19-2018

Integration error while building project in SDSoC

Hi,

When I was building a project in SDSoC, I am getting the following errors:


make: *** [all] Error 1    frontend_system             C/C++ Problem
make: *** [frontend.elf] Error 1    frontend             C/C++ Problem
recipe for target 'frontend.elf' failed    makefile    /frontend/Release    line 45    C/C++ Problem
SdsCompiler 83-5004: Build failed    frontend             C/C++ Problem
SdsCompiler 83-5019:compiler.deleteDefaultReportConfigs=false" '    frontend        line 0    C/C++ Problem
VPL 60-704: Integration error, problem implementing dynamic region, route_design ERROR    frontend             C/C++ Problem
VPL 60-806: Failed to finish platform linker    frontend             C/C++ Problem
VPL-4: Design failed to meet timing.    frontend             C/C++ Problem

 

Can anyone please suggest how to resolve these errors?

Thanks.

 

 

 

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9 Replies
Voyager
Voyager
313 Views
Registered: ‎10-23-2018

Re: Integration error while building project in SDSoC

@radhikamkr

Most of these look like they stem from the same root cause... look in frontend and resolve that error, and things will look much better.

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Visitor radhikamkr
Visitor
308 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

Can you suggest any possible errors?

The code is running fine in Vivado_HLS. But giving these errors in SDSoC.

 

Thanks.

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Xilinx Employee
Xilinx Employee
249 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Hi @radhikamkr

 

Looks like the design has got timing violations.

Please add explore directive and give it a try.

sds++ -xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}"

Refer below screenshot

xp_params_explore_directive.PNG

Best Regards,
Nutan
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Visitor radhikamkr
Visitor
239 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

Sorry,But what does this directive do?

Thanks.

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Xilinx Employee
Xilinx Employee
225 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Hi @radhikamkr

When there are timing violations in your design, it means that timing requirements were not met for all paths in your design.

If the Vivado router is run with the EXPLORE directive, it can add additional clock roots to a net in order to improve the quality of the results.

 

Best Regards,
Nutan
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Visitor radhikamkr
Visitor
223 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

I tried adding the directive. But of no use.

The functions when hardware accelerated individually, are working fine. The trouble comes when all the functions are called inside a function and the top function is hardware accelerated.

I am attaching my code below.

Can you please look into it if possible.

Thanks.

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Xilinx Employee
Xilinx Employee
207 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Hi @radhikamkr

Please send the timing report  *_timing_summary.rpt

 

Best Regards,
Nutan
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Visitor radhikamkr
Visitor
193 Views
Registered: ‎07-19-2018

Re: Integration error while building project in SDSoC

When I inline the functions the timing error is coming. When I remove it there is no timing error. But resource utilization is going up. Why is this happening?

Sorry, I couldn't locate the timing report.

Thanks.

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Xilinx Employee
Xilinx Employee
179 Views
Registered: ‎08-20-2018

Re: Integration error while building project in SDSoC

Hi @radhikamkr

In your project folder based on your build configuration, there will be a Debug or Release Folder, inside it, there should be _sds folder. You can find timing report inside that

Best Regards,
Nutan
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