UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer elaine.j.lee-2
Observer
1,252 Views
Registered: ‎05-14-2018

Issues on custom SDSoC platform

Hi all.  I’m new to using Xilinx tools and I’m having a very difficult time. I’m trying to create an SDSoC custom Hardware Platform (with custom IP blocks) to run application code on a zedboard. I’ve done the UG1236 Tutorial and am using UG1146. The tutorial specifically states at the beginning of the tutorial that the purpose is “… to create an SDSoC™ platform that can be used to accelerate software functions using the SDx™ Integrated Design Environment (IDE) tool“.  This is great because I can see how SDSoC works “under the hood” when you start out with only C/C++ code then select functions to “accelerate” but it is not a how to for a custom hardware platform (i.e. is the clock wizard a must?).

 

I have been able to generate a *.dsa file in Vivado (2017.4) with my custom IP block and it seems to have passed “validate_dsa”.

I’ve been able to open SDx 2017.4 and create a custom platform from the *.dsa file, add it to the custom repository and select it when I create an a new “SDx Project” type Application.  I’ve chosen the custom board I created, set system configuration to “standalone” and selected “Empty Application”. I then import the code from SDK 2017.4 that I used to test the Vivado design before creating the *.dsa file. 

 

But, I’m getting the following error when I build the project:

 SDSoC_Bld_Err.png

Where:

 ERROR: [VPL 60-341] Hardware accelerator integration failed. Aborting build_system. The following log file is available for debugging 'C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/p0/_vpl/ipi/vivado.log'. Contact your local Xilinx representative and provide the log file for further assistance.

ERROR: [VPL 60-806] Failed to finish platform linker

ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling 'C:/Xilinx/SDSoC/SDx/2017.4/bin/vpl  --iprepo C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/iprepo/repo  --iprepo C:/Xilinx/SDSoC/SDx/2017.4/data/ip/xilinx  --platform C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/system/export/system/system.xpfm  --temp_dir C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/p0  --output_dir C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/p0/vpl  --input_file C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/p0/.xsd/top.bd.tcl  --target hw   --save_temps  --kernels none --webtalk_flag SDSoC  --remote_ip_cache C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/ip_cache '

 

And in the “vivado.log” file it stops here:

 

INFO: [Common 17-83] Releasing license: Synthesis

79 Infos, 38 Warnings, 0 Critical Warnings and 0 Errors encountered.

synth_design completed successfully

synth_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:53 . Memory (MB): peak = 916.367 ; gain = 462.723

INFO: [Common 17-600] The following parameters have non-default value.

general.maxThreads

INFO: [Common 17-1381] The checkpoint 'C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/p0/_vpl/ipi/syn/syn.runs/synth_1/system_wrapper.dcp' has been generated.

INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb

report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 916.367 ; gain = 0.000

INFO: [Common 17-206] Exiting Vivado at Mon May 21 22:23:54 2018...

[Mon May 21 22:23:58 2018] synth_1 finished

wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:01:26 . Memory (MB): peak = 651.895 ; gain = 0.000

--- DEBUG: reset_param general.maxThreads

couldn't open "C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/p0/_vpl/ipi/syn/syn.runs/synth_2/.xocc_runmsg.txt": no such file or directory

    while executing

"open $cookie_file w"

    ("foreach" body line 22)

    invoked from within

"foreach _run $runs {

      # puts "--- DEBUG: run: [get_property NAME [get_runs $_run]]"

      set run_status [get_property STATUS [get_runs $_run]]

 ..."

    (procedure "check_synth_runs_status" line 6)

    invoked from within

"check_synth_runs_status $steps_log"

    (procedure "ocl_util::create_ocl_dcp" line 80)

    invoked from within

"ocl_util::create_ocl_dcp $dsa_info $utilization $config_info"

    (file "C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/p0/_vpl/ipi/ipirun.tcl" line 162)

INFO: [Common 17-206] Exiting Vivado at Mon May 21 22:23:58 2018...

le "C:/SDx_2017_4/Ontonet_pass2DSAv4/platforms/empty_test_app4/Debug/_sds/p0/_vpl/ipi/ipirun.tcl" line 162)

INFO: [Common 17-206] Exiting Vivado at Mon May 21 22:23:58 2018...

 

The tutorial at this point looks like this:

 

INFO: [Common 17-83] Releasing license: Synthesis

47 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.

synth_design completed successfully

synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 902.395 ; gain = 448.844

INFO: [Common 17-600] The following parameters have non-default value.

general.maxThreads

INFO: [Common 17-1381] The checkpoint 'C:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/emptINFO: [Common 17-1381] The checkpoint 'C:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gINFO: [runtcl-4] Executing : report_utilization -file zynq7_board_wrapper_utilization_synth.rpt -pb zynq7_board_INFO: [runtcl-4] Executing : rreport_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 902.395 ; gain = 0.reporINFO: [Common 17-206] Exiting Vivado at Mon May 21 16:26:38 2018...

[Mon May 21 16:26:39 2018] synth_1 finished

wait_on_run: Time (s): cpu = 00:00:00 ; elapsed = 00:02:12 . Memory (MB): peak = 573.379 ; gain = 0.000

--- DEBUG: reset_param general.maxThreads

Design is defaulting to impl run constrset: constrs_1

Design is defaulting to synth run part: xc7z020clg484-1

INFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tclINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/empty_app/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/INFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/empty_app/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zynq7_board/ip/zynq7_bINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/empty_app/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zynq7_board/ip/zynq7_boINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_INFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/empty_app/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zynq7_board/ip/zynq7_boaINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zyncINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/empty_app/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zynq7_board/ip/zynq7_boarINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zynINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/empty_app/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zynq7_board/ip/zynq7_board_processing_INFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zyINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/empty_app/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zynq7_board/ip/zynINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zINFO: [Project 1-454] Reading design checkpoint 'c:/VivadoSDK_2017_4/ug1236_SDSoC_Tutorial/lab1_zync_tcl_gen3/platform/empty_app/Debug/_sds/p0/_vpl/ipi/syn/syn.srcs/sources_1/bd/zynq7_boarINFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement

INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

INFO: [Project 1-479] Netlist was created with Vivado 2017.4

INFO: [Device 21-403] Loading part xc7z020clg484-1

INFO: [Project 1-570] Preparing netlist for logic optimization

 

What am I missing? Have I not defined or mis-defined something? Sadly it’s taken me a week to get to this point.

 

HELP!

0 Kudos
4 Replies
Moderator
Moderator
1,216 Views
Registered: ‎09-12-2007

Re: Issues on custom SDSoC platform

Can you post the DSA file, and tag me please ill take a look

Highlighted
Observer elaine.j.lee-2
Observer
1,209 Views
Registered: ‎05-14-2018

Re: Issues on custom SDSoC platform

Thank you for your quick response.

0 Kudos
Observer elaine.j.lee-2
Observer
1,183 Views
Registered: ‎05-14-2018

Re: Issues on custom SDSoC platform

For those of you who may be interested here is the background:

 

Our goal: To run an application with custom IP blocks (done in VHDL) on the Zedboard.

 

  1. Used Vivado 2017.4 to create a Custom IP block with VHDL as the source.
  2. Created a Vivado 2017.4 project that included the Custom IP block.   NOTE the Vivado project we used was based on Xilinx application note xapp1170 converted for 2017.4. We just substituted the FIFO block with our custom block that is a pass thru to verify everything works before installing the actual custom block.
  3. Tested design on Zedboard.
    1. Opened SDK 2017.4 from Vivado after “exporting hardware & bitstream”.
    2. Chose “hello world” template.
    3. Built, programmed FPGA, downloaded app and ran on Zedboard. Worked.
    4. Replaced “hello world” code with an axi dma example in the SDK install path, xaxidma_example_sg_poll.c.
    5. Built, programmed FPGA, downloaded app and ran on Zedboard. Worked.
  4. Followed instructions in UG1236 to:
    1. Create the DSA in Vivado 2017.4
    2. Create the software components for the platform in SDK 2017.4
    3. Create the custom platform using SDx IDE 2017.4
    4. Create SDx IDE project using the custom platform, empty application then importing the SDK 2017.4 code used to test the Vivado HW design before creating the SDSoC custom HW platform.
    5. SDx build fails.
0 Kudos
Explorer
Explorer
932 Views
Registered: ‎04-18-2017

Re: Issues on custom SDSoC platform

@elaine.j.lee-2, @stephenm

 

Have you found the solution for this? I am facing the same exact problem.

0 Kudos