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Contributor
Contributor
554 Views
Registered: ‎10-18-2018

Making a Submodule using SDSoC

Hello!

I want to make a sub-module for an image procesing application using SDSoC. My entire design is designed using Vivado, is it possible to export the SDSoC design as an IP/submodule in my current design?

 

Thanks & Regards,

Urvish

 

Best Regards,
Urvish
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6 Replies
Xilinx Employee
Xilinx Employee
516 Views
Registered: ‎08-20-2018

Re: Making a Submodule using SDSoC

urvish@htic

You want to integrate SDSoC design in your vivado design. Am I right?

Correct me if my understanding is wrong.

Best Regards,
Nutan
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Contributor
Contributor
508 Views
Registered: ‎10-18-2018

Re: Making a Submodule using SDSoC

Yes. You are right.
Best Regards,
Urvish
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Xilinx Employee
Xilinx Employee
494 Views
Registered: ‎08-20-2018

Re: Making a Submodule using SDSoC

Hi urvish@htic

After building your SDSoC project, you can go to debug/run folder (based on your active build configuration)

Navigate to _sds/p0/vivado/prj

You can see vivado project which will have sdsoc design integrated in it.

Please check if that is what you need.

Best Regards,
Nutan
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Contributor
Contributor
484 Views
Registered: ‎10-18-2018

Re: Making a Submodule using SDSoC

Hello @nutang,

I cannot see any folder named "vivado" in that directory. I can see some IP repositories being created. Can I export them into my Vivado design? If yes, how to do that?

Best Regards,
Urvish
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Xilinx Employee
Xilinx Employee
470 Views
Registered: ‎08-20-2018

Re: Making a Submodule using SDSoC

Hi urvish@htic

Looks like your SDSoC build is not completed or not successful.

The tool flow contains the step which creates the vivado project.

Best Regards,
Nutan
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451 Views
Registered: ‎10-17-2017

Re: Making a Submodule using SDSoC

Why not use HLS for the submodule ?