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Observer motebphd2018
Observer
451 Views
Registered: ‎05-31-2018

OpenCL Pinned memory on ZU9CG board (Zynq UltraScale+ MPSoC) not working

Dear all,

I am using ZU9CG board (Zynq UltraScale+ MPSoC). Currently, I am using OpenCL through SDx environment (Specifically SDSoC) for implementing an HPC application on my board.  

My understanding that is Xilinx support OpenCL specification 2.0 where for example OpenCL pinned memory concept is supported. The idea of the pinned memory as I understand is useful for OpenCL host and device that are shared a physical memory such as the ZU9CG board. So that we can apply the pinned memory using OpenCL API enqueueMapBuffer & enqueueUnmapMemObject . 

I could not find an example that works on FPGAs either on Xilinx examples website or on Google search. 

Therefore, I have tried to do that myself in the SDSoC environment. 

 

This is my host code :

/*****************************************************************/

#include "xcl2.hpp"
#define LENGTH (8)
using namespace std;

int main(int argc, char* argv[])
{
size_t vector_size_bytes = sizeof(int) * LENGTH;
vector<int, aligned_allocator<int>> source_a(LENGTH);

// OPENCL HOST CODE AREA START
//Getting Xilinx Platform and its device
std::vector<cl::Device> devices = xcl::get_xil_devices();
cl::Device device = devices[0];
std::string device_name = device.getInfo<CL_DEVICE_NAME>();
//Creating Context and Command Queue for selected Device
cl::Context context(device);
cl::CommandQueue q(context, device);
//Loading XCL Bin into char buffer
std::string binaryFile = xcl::find_binary_file(device_name,"vadd");
cl::Program::Binaries bins = xcl::import_binary_file(binaryFile);
devices.resize(1);
cl::Program program(context, devices, bins);


//Creating Kernel and Functor of Kernel
int err1;
cl::Kernel kernel(program, "vadd", &err1);
auto krnl_vadd = cl::KernelFunctor<cl::Buffer&>(kernel);

//Creating pinned Buffer in the shared DDR memory
cl::Buffer buffer_a(context, CL_MEM_READ_WRITE | CL_MEM_ALLOC_HOST_PTR , vector_size_bytes);

// host pointer to the pinned buffer
float *ptr= (float*)q.enqueueMapBuffer(buffer_a,CL_TRUE, CL_MAP_WRITE, 0,vector_size_bytes, 0,NULL, NULL);

// Fill the pinned bufer with initial data
cout<< " Before EnqueueNDRangeKernel ptr="<<ptr<<endl;
for(int i=0; i < LENGTH; i++){
ptr[i]=1;
}
cout<<endl;


// give the device the ownership of the buffer
q.enqueueUnmapMemObject(buffer_a, ptr, NULL, NULL );

//Running Kernel
cout<<endl;
cout<<"call the kernel"<<endl;
krnl_vadd (cl::EnqueueArgs(q, cl::NDRange(1,1,1), cl::NDRange(1,1,1)),
buffer_a);
cout<<"kernel finished"<<endl;
cout<<endl;

// read the data from the pinned memory using the host pointer
ptr =(float*) q.enqueueMapBuffer(buffer_a,CL_TRUE, CL_MAP_READ, 0,vector_size_bytes, 0,NULL, NULL);

cout <<"After the kernel execution ptr= "<<ptr<<endl;

//printing out the data from the kernel using the host pointer
for(int i=0; i < 8; i++){
cout<<ptr[i];
}
cout<<endl;

 

q.enqueueUnmapMemObject(buffer_a, ptr, NULL, NULL ); // give the device the ownership of the buffer
q.finish();

}

/*****************************************************************/

 

This is my Kernel:

/*****************************************************************/

#define N 8

__kernel void __attribute__ ((reqd_work_group_size(1, 1, 1)))
vadd(
__global int* a
) {


for(int i=0; i < 8; i++)
{
a[i] = a[i]+2;
}

return;
}

/*****************************************************************/

 

The output, when run this on my FPGA, is :

/*****************************************************************/

platform Name: Xilinx
Vendor Name : Xilinx
Found Platform
XCLBIN File Name: vadd
INFO: Importing ./vadd.xclbin
Loading: './vadd.xclbin'
xclAllocUserPtrBO called.. 0x137f79e0
Before EnqueueNDRangeKernel ptr=0x137fa000


call the kernel
kernel finished

After the kernel execution ptr= 0x137fa000
11111111

/*****************************************************************/

 

I expected the output to be 3 3 3 3 3 3 3 3

Not 1 1 1 1 1 1 1 1 which is the initials values in the pinned memory. 

This seems to me that the kernel does not get any access to the pinned memory.

Therefore, is that because Xilinx does not support this concept or my code is not correct?

Please, can anyone help me with this and give me an idea of how to apply this concept.

 

I really looking forward to your help. 

Thanks in advance.   

 

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6 Replies
Moderator
Moderator
403 Views
Registered: ‎08-20-2018

Re: OpenCL Pinned memory on ZU9CG board (Zynq UltraScale+ MPSoC) not working

Hi @motebphd2018 

Please let me know the SDSoC version

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
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Observer motebphd2018
Observer
394 Views
Registered: ‎05-31-2018

Re: OpenCL Pinned memory on ZU9CG board (Zynq UltraScale+ MPSoC) not working

Hi @nutang 

 

It is 2018.1

 

Thanks 

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Moderator
Moderator
382 Views
Registered: ‎08-20-2018

Re: OpenCL Pinned memory on ZU9CG board (Zynq UltraScale+ MPSoC) not working

Hi @motebphd2018 

Please refer below example

https://github.com/Xilinx/SDSoC_Examples/tree/2018.1/ocl/getting_started/wide_mem_rw_ocl

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
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Observer motebphd2018
Observer
376 Views
Registered: ‎05-31-2018

Re: OpenCL Pinned memory on ZU9CG board (Zynq UltraScale+ MPSoC) not working

Hi @nutang 

Thank you for your reply.

The example in  

https://github.com/Xilinx/SDSoC_Examples/tree/2018.1/ocl/getting_started/wide_mem_rw_ocl

is for wide memory implementation which is not what I am asking about. 

What I am asking about is the use of CL_MEM_ALLOC_HOST_PTR to create a pinned buffer that can be accessed from the host and the device. 

(cl::Buffer buffer_a(context,  CL_MEM_ALLOC_HOST_PTR , vector_size_bytes); )

My question is: does SDSoC or SDAccel support the use of a pinned buffer?

Because I am not getting the right results back.

 

 

0 Kudos
Moderator
Moderator
369 Views
Registered: ‎08-20-2018

Re: OpenCL Pinned memory on ZU9CG board (Zynq UltraScale+ MPSoC) not working

Hi @motebphd2018 

Yes, I am aware that your implementation is different. I just shared the implemetation for the reference.

Sorry I did not clear that before.

I will confirm if it supports pinned buffer in a while.

Best Regards,
Nutan
-------------------------------------------------------------------------------
Please don't forget to reply, kudo and accept as a solution
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Observer motebphd2018
Observer
361 Views
Registered: ‎05-31-2018

Re: OpenCL Pinned memory on ZU9CG board (Zynq UltraScale+ MPSoC) not working

Dear @nutang 

Thank you for your help.

I really appreciate that.

I am looking forward to your reply.

 

Regards

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