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Registered: ‎07-08-2016

SDSoC build error

Anyone has idea about how this error comes? The HLS step works fine.

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Xilinx Employee
Xilinx Employee
Registered: ‎07-13-2012

The error messages indicate there was a problem creating a block diagram for your design (in the form of

a Vivado IPI block diagram file). The input file use in this step is the apsys_0.xml file, which is found in the

folder <rest_of_path>/SDRelease/_sds/.llvm/apsys_0.xml.


The apsys_0.xml contains a graph of the design, including instantiated Vivado HLS IP and the data motion

network SDSoC created based on the IP as well as calls to the IP.


More information is needed to isolate the cause of the problem.


Would it be possible to attach:

- the apsys_0.xml file (this won't reveal any details of your design except connectivity)

- code snippets that shows how your accelerator function is defined (you can leave out details of the function of the body), including any pragmas in your code, especially for function arguments and interfaces

- code snippets that show the calling code of the accelerator

- any additional information you think might be relevant (are you specifying a TCL file for the GUI to use, launching Vivado HLS from the GUI to modify the design, or simply specifying a function to move to hardware and building the design)


If you are able to create a simplified version of your design with the same issue, can export the project (using File > Export),

and attach that, it would be easier for someone to reproduce the issue. You could simplify the design to remove any code

you don't want to make public or visible - a minimal design is fine. It's unlikely the problem is related to the implementation of the internals of the function.

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