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Participant gomo
Participant
5,197 Views
Registered: ‎07-18-2016

SDSoC compile filter2d of zcu102-base-trd-2016-2

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hi all,

      I download the zcu102-base-trd-2016-2 and according the introduce of link:http://www.wiki.xilinx.com/Zynq+UltraScale+MPSoC+Base+TRD+2016.2. And petalinux can build the image successfully. when I use SDSoC to compile the filter2d. I meet with error. The following is the info of error and attach the compile log.  BTW, the system.hdf(using in petalinux-build) is come from the ./apu/zcu102_base_trd/hardware/prebuild/export/zcu102_base_trd_wrapper.hdf.    

Thanks a lot!

 

 

problems.png

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Xilinx Employee
Xilinx Employee
6,315 Views
Registered: ‎07-13-2012

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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The message below suggests synthesis exited unexpectedly:

 

/opt/Xilinx/SDSoC/2016.2/Vivado/2016.2/bin/loader: line 164: 21262 Killed                  "$RDI_PROG" "$@"
Parent process (pid
21262) has died. This helper process will now exit
[Wed Aug 24 15:06:36 2016] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:03 ; elapsed = 00:22:18 . Memory (MB): peak = 1268.039 ; gain = 27.137 ; free physical = 6468 ; free virtual = 9735

 

What version of Ubuntu are you using? The release notes indicate Ubuntu 14.04.3 LTS is supported

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug1185-sdsoc-release-notes.pdf

 

It's possible there is an OS compatibility issue.

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8 Replies
Xilinx Employee
Xilinx Employee
5,188 Views
Registered: ‎08-01-2008

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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check this post you can find good suggestions
https://forums.xilinx.com/t5/SDSoC-Development-Environment/ERROR-VRFC-10-2063-Module-not-found-while-processing-module/td-p/703952
https://forums.xilinx.com/t5/SDSoC-Development-Environment/Error-building-application-with-c-callable-library-in-SDSoC/td-p/715040
Thanks and Regards
Balkrishan
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Xilinx Employee
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Registered: ‎08-02-2011

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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I would try pushing down to the _sds/p0_ipi directory and opening the Vivado project to see if there are any more details about what's wrong. Maybe need to try re-running synthesis from there.
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Xilinx Employee
Xilinx Employee
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Registered: ‎12-08-2011

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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Can you please look inside and/or attach the vivado.log file? It's not obvious from sds.log what has gone wrong.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-13-2012

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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Hi,

 

A couple suggestions based on the sds.log file attached.

 

1. SDSoC and the TRD are installed in the /opt folder, and you are also running the tools in the /opt folder. Please

    create the GUI workspace outside of the /opt folder and try again.

2. The sds.log file indicates synthesis failed. The error message suggests looking at the vivado.log file

/opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/p0/ipi/vivado.log

3. You can also look at the synthesis log file in /opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/p0/ipi/synth_1 for error messages.

4. In the Project Explorer, if you right click on the project name and open the C/C++ Build Settings dialog, in the SDS++ LINKER > Miscellaneous you can add the -verbose option to the Linker Flags text field, click OK, and build again to see more detailed messages in the Console. This just makes the output in the log files mentioned in items (2) and (3) above visible on the Console. 

 

Please try the above.

 

Regards,

 

[17:32:55] Starting synth_design
... [17:33:00] Starting RTL Elaboration : Time (s): cpu = 00:01:10 ; elapsed = 00:01:20 . Memory (MB): peak = 1333.883 ; gain = 450.840 ; free physical = 4366 ; free virtual = 8353
... [17:45:45] Start Applying 'set_property' XDC Constraints
... [17:46:20] Start RTL Component Statistics
... [17:46:20] Start RTL Hierarchical Component Statistics
... [17:46:20] Start Part Resource Summary
... [17:46:20] Start Parallel Synthesis Optimization  : Time (s): cpu = 00:14:30 ; elapsed = 00:14:41 . Memory (MB): peak = 2889.520 ; gain = 2006.477 ; free physical = 109 ; free virtual = 4136
... [17:46:20] Start Cross Boundary Optimization
... [17:46:30] Start Area Optimization
... [17:47:00] Start Timing Optimization
... [17:47:21] Start Applying XDC Timing Constraints
... [17:47:31] Start Technology Mapping
ERROR: [SDSoC 0-0]: Synthesis failed : status synth_design ERROR : progress 0%
INFO: [SDSoC 0-0] See /opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/p0/ipi/vivado.log for the context of the Vivado message above.
ERROR: [SDSoC 0-0] Exiting system_linker: Error when calling '/opt/Xilinx/SDSoC/2016.2/Vivado/2016.2/bin/vivado -mode batch -source "/opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/p0/ipi/top.impl.tcl"'
ERROR: [SDSoC 0-0] Exiting sds++ : Error when calling 'system_linker -cf-input /opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/.llvm/apsys_0.xml -cf-output-dir _sds/p0 -ip-db /opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/.cdb/xd_ip_db.xml -ip-repo /opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/iprepo/repo -sds-pf /opt/zcu102-base-trd-2016-2/apu/zcu102_base_trd:linux -bitstream -bit-name libfilter2d.so.bit -boot-files    -disable-ip-cache -mdev-no-swgen -mdev-no-xsd -sdsoc -sd-output-dir _sds/p0/sd_card -bit-binary -elf /opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/swstubs/libfilter2d.so'
sds++ log file saved as /opt/zcu102-base-trd-2016-2/apu/video_app/filter2d/SDRelease/_sds/reports/sds.log
ERROR: [SDSoC 0-0] Build failed
sds++ completed at Tue Aug 23 17:50:24 CST 2016

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Participant gomo
Participant
5,154 Views
Registered: ‎07-18-2016

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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Thanks all the reply at first!

I compile again in other computer. And the result is same.

1) I separate the SDSoC(/opt) and TRD(/home);

2) I added the -verbose option and got the more console information, Please see the attanched file of console.txt;

3) And I also attach the vivado.log and sds.log; 

 

In the file of vivado.log, I can see the following errors. And the .hdf file I used is come from the zcu102-base-trd-2016-2. 

 

Thanks a lot.

 

 

---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
WARNING: [Synth 8-207] constrained pin 'zcu102_base_trd_i/fmc_hdmi_input/v_vid_in_axi4s_1/inst/aresetn' not found
WARNING: [Synth 8-207] constrained pin 'zcu102_base_trd_i/fmc_hdmi_input/v_vid_in_axi4s_1/inst/vid_io_in_reset' not found
WARNING: [Synth 8-207] constrained pin 'zcu102_base_trd_i/tpg_input/v_vid_in_axi4s_0/inst/aresetn' not found
WARNING: [Synth 8-207] constrained pin 'zcu102_base_trd_i/tpg_input/v_vid_in_axi4s_0/inst/vid_io_in_reset' not found
INFO: [Synth 8-139] cannot merge instances zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from and zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MMADDR64.I_S2MM_DMA_MNGR/I_STS_MNGR/halted_clr_reg because of non-equivalent assertions
INFO: [Synth 8-139] cannot merge instances zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MMADDR64.I_S2MM_DMA_MNGR/I_STS_MNGR/halted_clr_reg and zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from because of non-equivalent assertions
INFO: [Synth 8-139] cannot merge instances zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from and zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MMADDR64.I_S2MM_DMA_MNGR/I_STS_MNGR/halted_clr_reg because of non-equivalent assertions
INFO: [Synth 8-139] cannot merge instances zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MMADDR64.I_S2MM_DMA_MNGR/I_STS_MNGR/halted_clr_reg and zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from because of non-equivalent assertions
INFO: [Synth 8-139] cannot merge instances zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from and zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MMADDR64.I_S2MM_DMA_MNGR/I_STS_MNGR/halted_clr_reg because of non-equivalent assertions
INFO: [Synth 8-139] cannot merge instances zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MMADDR64.I_S2MM_DMA_MNGR/I_STS_MNGR/halted_clr_reg and zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from because of non-equivalent assertions
INFO: [Synth 8-139] cannot merge instances zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from and zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MMADDR64.I_S2MM_DMA_MNGR/I_STS_MNGR/halted_clr_reg because of non-equivalent assertions
INFO: [Synth 8-139] cannot merge instances zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MMADDR64.I_S2MM_DMA_MNGR/I_STS_MNGR/halted_clr_reg and zcu102_base_trd_i/\fmc_hdmi_input/axi_vdma_1 /U0/\GEN_SPRT_FOR_S2MM.S2MM_LINEBUFFER_I/GEN_S2MM_FLUSH_SOF_LOGIC.GEN_FOR_ASYNC_FLUSH_SOF.RUNSTOP_AXIS_0_CDC_I_FLUSH_SOF/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.INPUT_FLOP.REG_PLEVEL_IN_cdc_from because of non-equivalent assertions
/opt/Xilinx/SDSoC/2016.2/Vivado/2016.2/bin/loader: line 164: 21262 Killed "$RDI_PROG" "$@"
Parent process (pid

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Xilinx Employee
Xilinx Employee
6,316 Views
Registered: ‎07-13-2012

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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The message below suggests synthesis exited unexpectedly:

 

/opt/Xilinx/SDSoC/2016.2/Vivado/2016.2/bin/loader: line 164: 21262 Killed                  "$RDI_PROG" "$@"
Parent process (pid
21262) has died. This helper process will now exit
[Wed Aug 24 15:06:36 2016] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:03 ; elapsed = 00:22:18 . Memory (MB): peak = 1268.039 ; gain = 27.137 ; free physical = 6468 ; free virtual = 9735

 

What version of Ubuntu are you using? The release notes indicate Ubuntu 14.04.3 LTS is supported

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug1185-sdsoc-release-notes.pdf

 

It's possible there is an OS compatibility issue.

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Participant gomo
Participant
5,128 Views
Registered: ‎07-18-2016

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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The OS is Ubuntu 14.04.4 LTS, I will download the Ubuntu 14.04.3 LTS and try again.

 

Thanks a lot.

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Participant gomo
Participant
5,103 Views
Registered: ‎07-18-2016

Re: SDSoC compile filter2d of zcu102-base-trd-2016-2

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Change OS to Ubuntu14.04.3, and compile the filter2d successfully. 

 

I don't understand what is the primary factor about this result.

 

Thanks a lot!

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