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lt23yuan_lm
Observer
Observer
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Registered: ‎07-11-2018

SDSoC keeps reporting "Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running"

Hello,

 

I created a C-callable IP from a HLS design package, and then invoked the generated *.a in the application. HLS IP packing and SDx IP generation are both done successful. However, when I built the application, the SDx keeps reporting messages like below. Then the build work cannot be finished forever. What might be the root cause?

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Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
Attempting to get a license: ap_sdsoc
Feature available: ap_sdsoc
INFO: [VPL 60-895]   Target platform: /mnt/HD/Xilinx201802/SDx/2018.2/platforms/zcu102/zcu102.xpfm
INFO: [VPL 60-423]   Target device: zcu102
INFO: [VPL 60-1032] Extracting DSA to /mnt/HD/workspace_sdsoc_ylt/ssd_engine/Debug/_sds/p0/vivado/.local/dsa
INFO: [VPL 60-251]   Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
[13:51:36] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[13:52:36] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[13:53:36] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[13:54:36] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[13:55:36] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[13:56:36] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[13:57:36] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.

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