12-12-2017 02:43 PM
I am starting an evaluation period of SDX for XILINX ZC702 family FPGA.
I am new.
I am completing some introductory tutorials. https://www.xilinx.com/html_docs/xilinx2017_2/sdsoc_doc/topics/tutorials/concept-lab-intro-to-sdsoc.html
I Run the initial build Lab1 from this tutorial. This is very simple matrix multiplication and matrix addition. I have been sitting here for 15 minutes and it is still only at 25%. Is this correct?
I am running on a I7 processor, 3GHz, 16GB ram Lattitude E6440. So reasonable specs.
I am curious for an actual project which will be much larger than this, how the build time will increase. This is not very practical, unless I am missing something important.
12-12-2017 03:54 PM
Slow is relative,
When it comes to creation of the hardware platform, one sees a slowdown to create a bitstream that can do something useful. The benefit is the resulting logic in the FPGA device is hundreds to thousands of times faster, and hundreds of times less power than processors running software.
Large designs may take all day, using up to eight cores, on really fast x86 machines. Medium size designs may take a few hours to target c/cpp code segments to be accelerated in hardware. If nothing is targeted to hardware it completes quite fast. One remains in software until everything is debugged. Then, moving modules as required to hardware to meet the needs of the application (for example 60 frames/sec 1080p HD video).
12-13-2017 02:00 AM
yes, as austin has already mentioned, synthesis can take a relatively long time.
A good method to cope with this is to use different build configurations. Personally, I usually use these 3:
The advantage of the first one is, that if you're building the project a second time while having done only minor changes, the build will usually finish really quick (~2 minutes for me), since SDx can skip expensive steps like creating the block diagram.
The built Project will usually (depending on your application) provide the same functionality, but just be a lot slower.
The second one is a good method for checking, if you're Hardware Functions are working as intended (e.g. verify that the initiation interval of a pipelined loop is adequate). This build configuration is also a lot faster, since it does not neet to create a bitstream. To give you an example: Building my current project takes around 2 hours, while the estimation takes around 10 minutes.
But you will quickly learn how to cope with the build times, it just needs some good time Management. :)
12-13-2017 09:03 AM
You can use the emulation to to test your system without generating the bitstream.
Users can also cache the IP in the platform
set_property dsa.ip_cache_dir [get_property ip_output_repo [current_project]] [current_project]
This should speed up the build alot
01-20-2018 09:50 PM
Hi everyone I want to know how slow will the example build will take? It seems the SDx
is dead down, and I dont know what is going on. Now it has taken 1hour, still 24%, as below. Is it normal or my SDx has problem?
****** vpl v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
INFO: [VPL 60-895] Target platform: D:/Xilinx/SDx/2017.4/platforms/zcu102\zcu102.xpfm
INFO: [VPL 60-423] Target device: zcu102
INFO: [VPL 60-251] Hardware accelerator integration...
01-20-2018 10:03 PM
Sorry about the last question, I found my PC goes in the sleep condtion automaticlly, by correctting the configuration the build can go smoothly, about 20 minutes.
10-18-2018 05:14 PM
03-07-2019 06:48 AM - edited 03-07-2019 07:38 AM