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Slow ddr memory access

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Newbie
Posts: 1
Registered: ‎07-18-2017
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Slow ddr memory access

Hi all,

My system frequently reads and writes the ddr memory to access small 2d-arrays with different sizes say, 15x8 pixels, 100*50 pixels, etc. (It is an image processing application). I used zero_copy and wrote a double loop to copy data from ddr memory to block ram for local access. But I still found that the runtime easily takes the order of million clock cycles (using sds_clock_counter() for 800MHZ arm).  Is this normal? Also, It seems that the compiler cannot generate burst read write code. In this case, how can I improve the memory access performance?

Device: Zynq 7Z100

SDK version: SDSoc 2015.4

Thanks a lot.


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Visitor
Posts: 23
Registered: ‎09-19-2017

Re: Slow ddr memory access

Hi cwng2002,

 

Vivado HLS can only infer bursts on specific access patterns in loops. If you're doing anything except the following for loop, bursts probably will not be inferred:

 

for(int I=0; I<N; I++)

    tmp[I] = data[I];

 

You can try running your application in QEMU/Emulation and see if your accelerator is bursting or not by looking at the AXI transactions it makes. 


Sam

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All Replies
Visitor
Posts: 23
Registered: ‎09-19-2017

Re: Slow ddr memory access

Hi cwng2002,

 

Vivado HLS can only infer bursts on specific access patterns in loops. If you're doing anything except the following for loop, bursts probably will not be inferred:

 

for(int I=0; I<N; I++)

    tmp[I] = data[I];

 

You can try running your application in QEMU/Emulation and see if your accelerator is bursting or not by looking at the AXI transactions it makes. 


Sam