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Visitor asenjo
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6,546 Views
Registered: ‎05-20-2016

Striving to get II=1

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Hi and thanks in advance for reading this,

 

I have a simple code implemented as a HW library that I got running following the samples/libmatrix example. In this matrix example theres is a simple loop:

 

..
..
for (index_d = 0; index_d < MSIZE; index_d++) {
#pragma HLS PIPELINE II=1 float product_term = in_A[index_a][index_d] * in_B[index_d][index_b]; result += product_term; }
..

that is successfully implemented with II=1.

 

My loop is just a little bit more complicated:

 

#pragma SDS data copy(posx[0:BLOCKSIZE])
#pragma SDS data access_pattern(posx:SEQUENTIAL)
#pragma SDS data mem_attribute(posx:PHYSICAL_CONTIGUOUS|CACHEABLE)
.. // Similarly, all other arrays have the same pragmas

void ComputeWhileFPGA( float posx[BLOCKSIZE], float posy[BLOCKSIZE], float posz[BLOCKSIZE], float dmas[BLOCKSIZE], float drs[BLOCKSIZE], float ob_accxyz[3] ) { float lox=0.0; float loy=0.0; float loz=0.0; for (int i=0; i<BLOCKSIZE; i++) { #pragma HLS PIPELINE II=1 float idr=1/sqrt(drs[i]); float nphi=dmas[i]*idr; float scale= nphi * idr * idr; float x=posx[i]*scale; lox += x; float y=posy[i]*scale; loy += y; float z=posz[i]*scale; loz += z; } ob_accxyz[0]=lox; ob_accxyz[1]=loy; ob_accxyz[2]=loz; }

 

 

But I get II=5. What I do not understand is the reason indicated in the .log file:

 

INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
WARNING: [SCHED 204-68] Unable to enforce a carried constraint (II = 1)
   between 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26) and 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26).
WARNING: [SCHED 204-68] Unable to enforce a carried constraint (II = 2)
   between 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26) and 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26).
WARNING: [SCHED 204-68] Unable to enforce a carried constraint (II = 3)
   between 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26) and 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26).
WARNING: [SCHED 204-68] Unable to enforce a carried constraint (II = 4)
   between 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26) and 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26).
INFO: [SCHED 204-61] Pipelining result: Target II: 1, Final II: 5, Depth: 143.

I would like to understand why there is here a "carried constraint" associated to the "lox" variable, but there is none for result in the mmult sample that get II=1. If anyone can shed some light here I would be grateful. Thanks.

 

 

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Xilinx Employee
Xilinx Employee
11,928 Views
Registered: ‎07-13-2012

Re: Striving to get II=1

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Xilinx Employee
Xilinx Employee
6,462 Views
Registered: ‎06-29-2015

Re: Striving to get II=1

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Hi asenjo,

 

This looks like a pure HLS question. I will give you a short answer, but if you have further clarifying questions please repost in the VivadoHLS forum: https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls

 

SDSoC calls VivadoHLS as a service (there is no special SDSoC-HLS version). So whatever HLS queries you have using SDSoC you can pose as general HLS questions. If you get questions regarding the #pragma SDS directives, you can see the HLS pragmas that SDSoC inserts into your code by looking at the <build_config>/_sds/vhls/<filename.c/cpp> file (warning, its rather large and your code will be at the bottom).

 

However, to answer your question look at the message VivadoHLS outputs:

 

WARNING: [SCHED 204-68] Unable to enforce a carried constraint (II = 1)
   between 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26) and 'fadd' operation ('lox', /users/ra15126/parallel_for_xilinx/ieBarnesHut/libBH/bhHW.cpp:26).

 

It clearly says that you have a loop carried constraint. Which means between iterations of the loop you have a dependency. In more simpler terms this means that the value of the previous iteration of the loop is used in the next iteration. Therefore pipelining is not possible, since the next iteration depends on the value from the previous. Pipelining implies that you can have multiple iterations of your loop executing at the same time, which isnt possible if there are inter-iteration dependencies. In your code, that lox variable is summing the values (lox += x) which depends on the value in lox from the previous loop. 

 

Sam

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Xilinx Employee
Xilinx Employee
11,929 Views
Registered: ‎07-13-2012

Re: Striving to get II=1

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