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Explorer
Explorer
4,650 Views
Registered: ‎01-04-2013

about external port Unspecified I/O Standard

Hello everyone,

I had a project in vivado 2015.4,its diagrammatic sketch like below

 QQ截图20160830151932.png

I made one of the Master port of Interconnect0 as external port,and used it in my top level

Then I executed the command "sdsoc::pfm_axi_port $pfm M03_AXI axi_interconnect_0 M_AXI_GP" when created pfm of my platform.

But when I generated bitstream in sdsoc , I got the error like below

 

QQ截图20160830153222.png

 

I guess that the vivado tool make the block design as the top level instead of mine,so the axi external port are acted as pin

 

Can anybody help me ?

 

Thanks a lot

Best wishes.

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2 Replies
Teacher muzaffer
Teacher
4,646 Views
Registered: ‎03-31-2012

Re: about external port Unspecified I/O Standard

vivado creates a BD wrapper module and any ports which you make "external" are propagated to the wrapper too so they become pins. If you want to include user-logic the way you show, you have two options:
* package your user-logic as IP and instantiate it in your BD and connect to the m03_axi in there.
* don't let Vivado manage the top level module and remove the ports from the top level port list and instantiate your module at top level.

The latter is what you are doing partially. I suggest that you change your design by packaging your axi slave to include it in BD and let Vivado manage the top level wrapper.
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Xilinx Employee
Xilinx Employee
4,643 Views
Registered: ‎08-01-2008

Re: about external port Unspecified I/O Standard

check this ARs
http://www.xilinx.com/support/answers/56609.html
Thanks and Regards
Balkrishan
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