08-30-2016 12:39 AM
I had a project in vivado 2015.4,its diagrammatic sketch like below
I made one of the Master port of Interconnect0 as external port,and used it in my top level
Then I executed the command "sdsoc::pfm_axi_port $pfm M03_AXI axi_interconnect_0 M_AXI_GP" when created pfm of my platform.
But when I generated bitstream in sdsoc , I got the error like below
I guess that the vivado tool make the block design as the top level instead of mine,so the axi external port are acted as pin
Can anybody help me ?
Thanks a lot
08-30-2016 01:02 AM
08-30-2016 01:19 AM