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Participant engsci
Participant
452 Views
Registered: ‎04-22-2016

pragma HLS loop_tripcount DOES impact synthesis

I've been analyzing an image processing hardware block of mine and have noticed that the

#pragma HLS loop_tripcount min=640

does have a significant impact on synthesis results from Vivado HLS - which is in contradiction to the official documentation by Xilinx available here: https://www.xilinx.com/html_docs/xilinx2018_2/sdaccel_doc/pragma-hls-loop_tripcount-sty1504034367099.html

 

In the following short snippet:

void function (ap_uint<8> Input[], ap_uint<8> Output[], int rows, int cols){

    for (int y = 0; y < rows; y++){
        for(int x = 0; x < cols; c++}{
#pragma HLS PIPELINE
#pragma HLS loop_tripcount min = 640
         
             // Code that stores incoming pixels into Linebuffer
 
       }
    }
} 

If the #pragma HLS loop_tripcount isn't present, HLS is unable to pipeline with an II = 1, at best it can achieve II = 2. I assume this is because, as cols is a variable to the function, it could be "1" which would be the edge case where there is a carrier dependency blocking the reading-in and storing of pixels into a Linebuffer and the fetching of pixel values from that same Linebuffer at the same index?

 

 

I just thought this would be useful to know as I spent a large amount of time trying to figure out the differences between two almost identical designs that only differed with this (which I didn't think played any role in synthesis).

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