UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer anjali@8
Observer
1,258 Views
Registered: ‎05-04-2018

reVISION stack

hello,
I was trying to execute an example from xfopencv design examples using reVISION platform zcu104. I am doing it through the terminal using the makefile. It works fine till the command comes "creating Vivado project and starting FPGA synthesis" after which it says synthesis is running and the PC gets hanged. After which I have to reboot my PC.
Alternatively I also tried doing it with sdx GUI and there also I am encountering the same problems. I tried executed some of the examples and in all of them I am facing this issue.
Please, help me resolve this issue.

 


****** vpl v2017.4 (64-bit)
  **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-895]    Target platform: /home/ignko-train/zcu104_rv_ss/zcu104_rv_ss.xpfm
INFO: [VPL 60-423]   Target device: zcu104_rv_ss
INFO: [VPL 60-251]   Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
[14:08:05] Synthesis is running.
[14:09:05] Synthesis is running.
[14:10:07] Synthesis is running.
[14:11:13] Synthesis is running.
[14:12:14] Synthesis is running.
[14:13:20] Synthesis is running.
.....

Thank you!
Anjali

0 Kudos
7 Replies
Moderator
Moderator
1,240 Views
Registered: ‎09-12-2007

Re: reVISION stack

Can you step us through exactly what you are doing. I can try replicate your steps

0 Kudos
Observer anjali@8
Observer
1,236 Views
Registered: ‎05-04-2018

Re: reVISION stack

I downloaded the xfopencv design examples from github. I also downloaded the reVISION platform zcu104_rv_ss.

I selected an example accumulate that was given in the directory and from the terminal I executed the makefile to get the .elf file.

But whenever the command "Creating the vivado project and starting FPGA synthesis" is coming my PC is getting hanged and then it stops responding.

I have tried this with other examples also but same thing is happening.

 

Thank you

Anjali

0 Kudos
Visitor vandenplas
Visitor
1,216 Views
Registered: ‎11-02-2017

Re: reVISION stack

I need help also as I cant get the revision stack to compile or run

 

I get a platform error ,,I really need some help

 

0 Kudos
Visitor vandenplas
Visitor
1,214 Views
Registered: ‎11-02-2017

Re: reVISION stack

I get this message

 

WARNING: [DMAnalysis 83-1005] Invalid clock id 2 for platform revision

WARNING: [DMAnalysis 83-1005] Invalid clock id 2 for platform revision

WARNING: [DMAnalysis 83-1005] Invalid clock id 2 for platform revision

INFO: [DMAnalysis 83-4497] Analyzing callers to hardware accelerators...

INFO: [DMAnalysis 83-4444] Scheduling data transfer graph for partition 0

WARNING: [DMAnalysis 83-1005] Invalid clock id 2 for platform revision

ERROR: [DMAnalysis 83-4503] No M_AXI_GP port found in the platform!

ERROR: [DMAnalysis 83-4445] Failed scheduling data transfer graph!

0 Kudos
Observer anjali@8
Observer
1,199 Views
Registered: ‎05-04-2018

Re: reVISION stack

Hey stephen,
Did you figured out the issue?

Thanks!
0 Kudos
Adventurer
Adventurer
1,012 Views
Registered: ‎04-24-2012

Re: reVISION stack

Hi,

You need the license that comes with the ZCU104 board, otherwise Vivado will fail to generate the RTL (the ZCU104 board definition have new added IP licensed for the ZCU104 platform) and you'll have those errors as a result.

/* Don't forget to give kudos and/or accept as a solution */
0 Kudos
Moderator
Moderator
996 Views
Registered: ‎09-12-2007

Re: reVISION stack

Sounds like the PFM properties in your platform were not set correctly.

Can you post your PFM properties that you used with a screenshot of your BD in Vivado?

0 Kudos