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daichong
Observer
Observer
1,156 Views
Registered: ‎03-13-2018

reVision Getting Started failed

When I follow the steps in the Web page

http://www.wiki.xilinx.com/reVISION%20Getting%20Started%20Guide%202017.4

to compile the Optical Flow demo, the following error occurs, how can I solve it? My SDSOC is 2017.4, Vivado comes with the SDSOC installation. I had the same error when running this demo in Windows 10 and Linux .

 

 

INFO: [VPL 60-895]    Target platform: D:/SDx_project/zcu102_es2_rv_ss\zcu102_es2_rv_ss.xpfm
INFO: [VPL 60-423]   Target device: zcu102_es2_rv_ss
INFO: [VPL 60-251]   Hardware accelerator integration...

===>The following messages were generated while  creating FPGA bitstream. Log file:D:/SDx_project/of2/Release/_sds/p0/_vpl/ipiivado.log :
ERROR: [VPL 5-336] This command cannot be run, as the BD-design is locked. Locked reason(s):
* Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
List of locked IPs: 
zcu102_es2_rv_ss_mipi_csi2_rx_subsystem_0_0
zcu102_es2_rv_ss_v_mix_0_0
zcu102_es2_rv_ss_v_proc_ss_csc_0
zcu102_es2_rv_ss_v_proc_ss_scaler_1
zcu102_es2_rv_ss_v_proc_ss_scaler_0
2.png
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3 Replies
wdlctc
Newbie
Newbie
1,080 Views
Registered: ‎06-21-2018

I met the same problem as yours. May someone fix it.

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diego73
Adventurer
Adventurer
1,030 Views
Registered: ‎04-24-2012

The solution is to add the license that comes in your the ZCU102 platform, that license will unlock the usage of those IPs that are causing you a problem.

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zhanghao270
Visitor
Visitor
780 Views
Registered: ‎07-18-2018

indeed, but how can I get  the license file from the Xilinx website?

I just could not find the entry.

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