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Visitor darthsimpson
Visitor
506 Views
Registered: ‎10-05-2018

reVision availabilty for the Ultra96

HI,

 

Does anyone know with reVision and some sample examples will be available for the Ultra96?

 

THanks,

 

Iain

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4 Replies
Xilinx Employee
Xilinx Employee
429 Views
Registered: ‎08-20-2018

Re: reVision availabilty for the Ultra96

Hi @darthsimpson

We do not have examples for Ultra96.

However, as Ultra96 is based on Xilinx Zynq UltraScale+ MPSoC. You can refer below examples.

https://github.com/Xilinx/reVISION-Getting-Started-Guide/blob/master/README.md

 

 

Best Regards,
Nutan
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Visitor darthsimpson
Visitor
419 Views
Registered: ‎10-05-2018

Re: reVision availabilty for the Ultra96

Hi nutang

So should it be easy to re-port the reVision examples to the Ultra96?

Or maybe wait for 2018.3, in which ive been told reVision on Ultra96 will be supported.

Also see the following thread....

https://xilinx2018.hackster.io/t/xilinx-revision-support-on-ultra96/870

Many thanks

DarthS

 

 

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Visitor darthsimpson
Visitor
276 Views
Registered: ‎10-05-2018

Re: reVision availabilty for the Ultra96

Ive being trying to comppile for the Ultra96 and get the following error for the opticalflow example surrounding the DMA implementation.... any ideas on how to fix this?

D:\ws_of\opticalflow\Release\_sds\.llvm>opt -disable-output -mem2reg -basicaa -XidanePass --platform ultra96 --dmclkid 3 --repo D:/ws_of/opticalflow/Release/_sds/.cdb/xd_ip_db.xml --dmdb D:/Xilinx/SDx/2018.2/data/DM.db -os linux -processor cortex-a53 -partition 0 0<sds_all.o
INFO: [DMAnalysis 83-4494] Analyzing hardware accelerators...
INFO: [DMAnalysis 83-4497] Analyzing callers to hardware accelerators...
INFO: [DMAnalysis 83-4444] Scheduling data transfer graph for partition 0
INFO: [DMAnalysis 83-4446] Creating data motion network hardware for partition 0
INFO: [DMAnalysis 83-4448] Creating software stub functions for partition 0
INFO: [DMAnalysis 83-4450] Generating data motion network report for partition 0
INFO: [DMAnalysis 83-4454] Rewriting caller code
Creating block diagram (BD)
Creating top.bd.tcl
ERROR: [CF2XD 83-1322] Cannot allocate 'ultra96' interrupt port1
ERROR: [CF2XD 83-2396] Exhausted number of available interrupts. Consider employing axi_dma_simple or zero_copy datamovers.
ERROR: [CF2XD 83-2009] An error has occurred during generation of the system block diagram. For more information, please look for additional ERROR messages in the console and in log files.
Error generating intermediate design file top.xml
Error creating IPI .bd design file, exiting
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling 'D:/Xilinx/SDx/2018.2/bin/sdx_link -cf-system D:/ws_of/opticalflow/Release/_sds/.llvm/apsys_0.xml -cf-db D:/ws_of/opticalflow/Release/_sds/.cdb/xd_ip_db.xml -xpfm D:/Learn/reVision/Ultra96-2018-2/ultra96/ultra96.xpfm -multi-clks -trace-buffer 1024 -quiet'
sds++ log file saved as D:/ws_of/opticalflow/Release/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed

make: *** [libopticalflow.so] Error 1

06:24:20 Build Finished (took 4m:18s.639ms)

 

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Explorer
Explorer
263 Views
Registered: ‎10-21-2015

Re: reVision availabilty for the Ultra96

Hi 

Your platform doesn't have available interrupts.

Make sure your vivado design has xlconcat ips connected to pl_ps_irq0/1

And check  your script  to create dsa is correct for interrupt

 

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