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Participant eejlny
Participant
260 Views
Registered: ‎05-05-2015

sdsoc hangs with more than one FPGA core and cacheable memory

Hello,

We have a sdsoc project 2018.1 on the zcu102 board that works correctly if one host thread calls two hardware cores in parallel using async/wait statements. This works correctly with memory allocated with sds_alloc and sds_alloc_non_cacheable.

If this project is modified so that there are two host threads working in parallel and each of them calls one hardware core independently of the other then this works correctly if the memory is allocated with sds_alloc_non_cachable. However if the memory is allocated with sds_alloc then only the first hardware core works while the second hangs like if it is not able the access cache. This happens using either the HP or the HPC ports.

I am wondering if there is a known limitation around this usage model ?

Thanks, 

 

 

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2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
234 Views
Registered: ‎08-20-2018

Re: sdsoc hangs with more than one FPGA core and cacheable memory

Hi @eejlny

Are you creating two hardware instances?

Best Regards,
Nutan
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Participant eejlny
Participant
229 Views
Registered: ‎05-05-2015

Re: sdsoc hangs with more than one FPGA core and cacheable memory

yes, I have verified in Vivado that the right number of hardware instances is created.

There is file called kernel.cpp that looks like this. The idea is that there two host threads calling function1 and function2 in parallel.

function1(....)

{

....

#pragma SDS resource(1)
#pragma SDS async(1)
spmm_simple7(rowPtr_int, columnIndex_int, values_int, y_int, x, row_size,line_count, nnz_int, error_condition);

#pragma SDS wait(1)

....

}

function2(....)

{

....

#pragma SDS resource(2)
#pragma SDS async(2)
spmm_simple7(rowPtr_int, columnIndex_int, values_int, y_int, x, row_size,line_count, nnz_int, error_condition);

#pragma SDS wait(2)

....

}

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