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Visitor nila
Visitor
201 次查看
注册日期: ‎12-18-2018

生成platform时xlconcat出错 is not the least significant available port on instance 'xlconcat_0', expected In2

使用Zedboard,vivado 2017.4,要生成一个带AXI HP的platform,在生成.dsa时出现下面这个错:

write_dsa -force E:/xilinx/code_sdx/AXI_DMA/AXI_DMA/AXI_DMA.srcs/sources_1/bd/AXI_DMA/AXI_DMA.dsa
INFO: [Vivado 12-4895] Creating DSA: E:/xilinx/code_sdx/AXI_DMA/AXI_DMA/AXI_DMA.srcs/sources_1/bd/AXI_DMA/AXI_DMA.dsa ...
ERROR: [SDSoC-pfm-10] ERROR: pfm_irq - port 'In0' is not the least significant available port on instance 'xlconcat_0', expected In2
ERROR: [SDSoC-pfm-10] ERROR: pfm_irq - port 'In1' is not the least significant available port on instance 'xlconcat_0', expected In2
INFO: [Vivado 12-5881] Successfully generated hpfm file
INFO: [Vivado-projutils-8] Tcl script 'rebuild.tcl' generated in output directory 'C:/Users/linjq/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6196-linjq-PC/dsa/prj'

INFO: [Vivado-projutils-17] Please note that the -paths_relative_to switch was specified, hence the project source files will be referenced wrt the
path that was specified with this switch. The 'origin_dir' variable is set to '.' in the generated script.

WARNING: [Vivado-projutils-10] Found source(s) that were local or imported into the project. If this project is being source controlled, then
please ensure that the project source(s) are also part of this source controlled data. The list of these local source(s) can be found in the generated script
under the header section.

INFO: [Vivado 12-4896] Successfully created DSA: E:/xilinx/code_sdx/AXI_DMA/AXI_DMA/AXI_DMA.srcs/sources_1/bd/AXI_DMA/AXI_DMA.dsa
write_dsa: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1389.129 ; gain = 54.594
E:/xilinx/code_sdx/AXI_DMA/AXI_DMA/AXI_DMA.srcs/sources_1/bd/AXI_DMA/AXI_DMA.dsa

原理图如下,请看看是什么问题?谢谢!

AXI_DMA.jpg

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Voyager
Voyager
160 次查看
注册日期: ‎10-24-2018

回复: 生成platform时xlconcat出错 is not the least significant available port on instance 'xlconcat_0', expected In2

@nila

This sounds similar to your problem... https://forums.xilinx.com/t5/SDSoC-Environment-and-reVISION/Not-able-to-generate-hw-platform/td-p/715794

If so, mark solution as accepted.

 

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Visitor nila
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123 次查看
注册日期: ‎12-18-2018

回复: 生成platform时xlconcat出错 is not the least significant available port on instance 'xlconcat_0', expected In2

@xilinxacct

Thanks for your reply.But it's a little different from that.

I past the TCL below:

set intVar []
for {set i 0} {$i < 16} {incr i} {
lappend intVar In$i {}
}
set_property PFM.IRQ $intVar [get_bd_cells /xlconcat_0]

also have "Export Hardware"

but when I use the TCL:

write_dsa -force E:/xilinx/code_sdx/AXI_DMA/AXI_DMA/AXI_DMA.srcs/sources_1/bd/AXI_DMA/AXI_DMA.dsa

it's show the error message.

Is there any other possibility of causing this mistake?Thanks!

 

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