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注册日期: ‎05-24-2017

ERROR: [VPL 18-1000] Routing results verification failed due to partially-conflicted nets

 

[11:13:59] Phase 10 Verifying routed nets
[11:14:47] Phase 11 Depositing Routes


ERROR: [VPL 18-1000] Routing results verification failed due to partially-conflicted nets (Up to first 10 of violated nets): 
pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][194]_i_2_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][197]_i_2_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][199]_i_2_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][215]_i_2_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][23]_i_3_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][242]_i_2_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][272]_i_2_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][288]_i_1_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][292]_i_2_n_0 pfm_top_i/dynamic_region/memory_subsystem/inst/interconnect/interconnect_s00_axi/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum[data][302]_i_2_n_0
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, route_design ERROR
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [XOCC 60-398] vpl failed
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
../../../utility/rules.mk:128: recipe for target 'xclbin/pcaf_fpga.hw.xilinx_vcu1525_dynamic_5_1.xclbin' failed
make: *** [xclbin/pcaf_fpga.hw.xilinx_vcu1525_dynamic_5_1.xclbin] Error 1

I got this error after a long run for the build of my kernel.

The violations seem related to the DDR bank interface.

How should I debug this issue.

Thanks.

 

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Moderator
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注册日期: ‎11-05-2010

回复: ERROR: [VPL 18-1000] Routing results verification failed due to partially-conflicted nets

1. 尝试采用不同的Implementation direcitve试一下.

2. 导出vivado implementation的中间文件, 比如XX_place.dcp. 

    在Vivado中打开这个dcp文件,运行route_design后查看布线问题的Net.

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回复: ERROR: [VPL 18-1000] Routing results verification failed due to partially-conflicted nets

@hongh

 

Thanks for reply.

I opened the dcp file and attached the timming file.

The error generated during the routing stage.But there is no hint about the user logic in the kernel.

What should I do?

 asfasdfas.JPG

 

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回复: ERROR: [VPL 18-1000] Routing results verification failed due to partially-conflicted nets

Hi, @mathmaxsean ,

Did you meet this issue with the example design in 2018.2 targeting platform VCU1525?

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回复: ERROR: [VPL 18-1000] Routing results verification failed due to partially-conflicted nets

@hongh

 

I didn't use example. It's my own code.

I work on the SDACCel 2018.2 with VCU1525.

There is a array that I tried to be partitioned using the "#pragma HLS ARRAY_PARTITION variable=...   cyclic factor = 192..."

Actually I just need a factor value as 192.

But the compiler complains: "WARNING: [XOCC 204-69] Unable to schedule 'load' operation ('query_or_x_0_V_load_5', / pcaf_fpga.cpp:135) on array 'query_or_x_0_V' due to limited memory ports. Please consider using a memory core with more ports or partitioning the array 'query_or_x_0_V'.

INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 32, Depth = 99."

After I changed the factor value to 240, it still complained the same issue. I am very sure the 192 is enough for the value of factor.

Then I tried using "complete" instead of  "cyclic factor =" to partiton the array, which has 960 elements.

This time there is no complains but the timming violation happens as I post before.

 Any suggestion?

 

Thanks

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回复: ERROR: [VPL 18-1000] Routing results verification failed due to partially-conflicted nets

Hi, @mathmaxsean ,

The unrouted issue may be caused by too much logic usage, because the memory system generated in dynamic region will share the resource with your kernel resource.

You can try to analyze the logic utilization of kernel first when the performance is achieved. 

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