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legendbb
Voyager
Voyager
1,591 Views
Registered: ‎07-28-2008

10G/25G subsystem, how to bring out gt_refclk?

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I have a design with 10G/25G subsystem (including shared logic in core) in block design.

Is there a way to bring out gt_refclk to share with other Quads?

The port gt_reclk_out is after BUFGT_GT

 

Or maybe I have to change the core to "Include Shared Logic in example design" then add example design into block design. That complicates design hierarchy.

 

Please comment,

 

Thanks,

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venkata
Moderator
Moderator
2,136 Views
Registered: ‎02-16-2010
apologies. It is my mistake in reading your query.

For me, it seems you need to set "Shared logic in example", keep the IBUFDS_GTe4 and QPLL outside of the IPI design and bring in the shard logic ports to IPI design.
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venkata
Moderator
Moderator
1,583 Views
Registered: ‎02-16-2010

which vivado version are you using? In vivado 2017.4, I can see gt_refclk_out port at the IP interface.10g_25g.PNG

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legendbb
Voyager
Voyager
1,580 Views
Registered: ‎07-28-2008

I'm on 2017.3 can see gt_refclk_out too.

I assume gt_refclk_out after BUFG_GT can't be as reference clock source for other Quads,

Only gt_refclk can be used.

 

Following code is from example design without shared logic in core.

gt_refclk.PNG

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venkata
Moderator
Moderator
2,137 Views
Registered: ‎02-16-2010
apologies. It is my mistake in reading your query.

For me, it seems you need to set "Shared logic in example", keep the IBUFDS_GTe4 and QPLL outside of the IPI design and bring in the shard logic ports to IPI design.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post