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Registered: ‎10-31-2016

7 Series GTP IBIS AMI 3.0 Model Questions (PCIe simulation in HyperLynx)

I am working on validating a PCIe channel in HyperLynx 9.4 using the 7 Series IBIS AMI 3.0 model on a Windows 10 machine and had a few questions.


When running the IBIS AMI Channel Analyzer, it appears that the mode may be missing the ability to invert the tap weights.  I looked at the .ami file as well and noticed that it did not contain the necessary parameter for inverting the tap weights:


Based on the datasheet, there should be a setting called “TXPRECURSORINV” to do so:



The only available weights are positive coefficients:



I gathered this off of the following datasheet:

The transceiver TX configuration setup begins on page 156.


  1. What is an appropriate simulation time for this model?  The total simulation time is around 20-30 minutes for 1 million bits and I wanted to make sure that sounded right.


  1. Is there a way to manually specify the clock recovery circuit?  The receiver model's clock recovery appears to be half a phase out of synch based on the time domain analysis result in the HyperLynx IBIS AMI Channel Analyzer:


When I manually disabled the model's clock and had the EDA tool automatically detect the clock, the results were fine:



On an interesting note, the v1.0 model of this transceiver works fine.  Has anything changed in this model that could cause the clock recovery to be out of phase?






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5 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎07-31-2012

Is there a way to manually specify the clock recovery circuit?

I dont think you can play around with the CDR parameters in the AMI model. The paramters which you can configure are mentioned in this link in Pg 10 -

Read through this to understand the IBIS-AMI models better.

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
Registered: ‎10-31-2016

Hi Anirudh,


Thank you for your reply.  In HyperLynx, there is a way to manually ignore the receiver CDR.  In it's place, HyperLynx will create one itself based on the received signal.  This is how I was able to correct the eye in HyperLynx.  Is it possible to investigate this further to see if something might be wrong with the model's CDR?


I have read this document and this is not the model that I am referring to.  The GTP is different that the GTX from my understanding, but please correct me if I am wrong.  Also, I understand that the parameters in the document are available to modification.  My question is why you cannot invert the pre-cursor like you can on the actual transceiver?


Also, the link for additional resources in that document is broken:



Also, what is a reasonable simulation time for this model on a single channel?

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Registered: ‎02-15-2018

Dear All, Could you please help me with the following issue:



​please send IBIS-AMI of model "7-Series IBIS-AMI models". Goal is a  post-topological modeling of PCIe in HyperLynx.


​If possible that for FPGA Artix 7 XC7A200T-2FFG1156I   PCIe x4 is connected with BANK213 in below order::

# PCIe Lane 0
set_property LOC GTPE2_CHANNEL_X0Y0 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
# PCIe Lane 1
set_property LOC GTPE2_CHANNEL_X0Y1 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
# PCIe Lane 2
set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
# PCIe Lane 3
set_property LOC GTPE2_CHANNEL_X0Y3 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]

# GTP Common Placement
set_property LOC GTPE2_COMMON_X0Y0 [get_cells {inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gtp_common.gtpe2_common_i}]

​Project: Interface paddleboard PCIe x4 with GbEthernet for coupling of comminication modules.


​Hope to hear from you soon.

Thank you!​

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Xilinx Employee
Xilinx Employee
Registered: ‎06-01-2017


You can access the 7 series IBIS-AMI lounge here:

If you don't already have access, submit a request and that should be approved in a day.


The IBIS-AMI model is GT specific but not location specific. You can find the GTP IBIS-AMI model download link in the 7 series lounge. The model is not protocol specific either, set the AMI analysis to your targeted line rate and data pattern, and that will provide the performance outlook for your application.


The IBIS-AMI model package includes an user guide which should give you the steps needed to start a channel simulation.

Don’t forget to reply, kudo, and accept as solution.
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Xilinx Employee
Xilinx Employee
Registered: ‎11-29-2007


these two are limits of the GTP IBIS-AMI model:

1) the pre-cursor inversion is missing. For typical TX equalization the pre-cursor should not be inverted.

2) eye offset: the IBIS-AMI model generates the recovered clock tick at the wrong position. If your EDA tool uses the clock tick to build the signal eye, the eye results with 1/2 UI offset.

There is no plan to fix the model and the only possible workaround is to tell HL to neglect the clock tick reference - as you correctly did already. HL will refer to its own recovered clock based on received signal.


My personal curiosity: which channel requires to invert the TX pre-cursor?


thanks, kind regards,


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