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Observer prakashdrj
Observer
907 Views
Registered: ‎07-12-2016

[7 Series GTX] RXUSRCLK2, RXUSRCLK, and RXOUTCLK turned off abnormally

 

What are the possible reasons that can cause RXUSRCLK2, RXUSRCLK, and RXOUTCLK turned OFF abnormally in 7 Series GTX? It seems that RXOUTCLK from GTX is turned off without any apparent reason and hence RXUSRCLK2, RXUSRCLK are also turned off.

 

Followings are the status of relevant signals,

RXUSERRDY = 1'b1,

[RX/TX]PD = 2'b10,

[TX/RX]RESETDONE = 1'b1,

TXELECIDLE = 1'b1,

TXDETECTRX = 1'b0,

RXOUTCLKSEL = 3'b010, 

RXSYSCLKSEL = 2'b11

QPLLRESET = 1'b0,

All Reset related signals are low.

 

RXOUTCLK gets turned off as soon as [RX/TX]PD is change from 2'b00 to 2'b10 with TXELECIDLE = 1'b1.

 

What can cause this issue? Does this have anything to do with signalling on GTX[RXP/RXN]?

0 Kudos
5 Replies
Moderator
Moderator
878 Views
Registered: ‎07-30-2007

Re: [7 Series GTX] RXUSRCLK2, RXUSRCLK, and RXOUTCLK turned off abnormally

The PD in RXPD stands for power down.  It will turn off the clocks.  It is an input to the GT so it is something you should have control over.  Perhaps you're using some ip (PCIE) that is doing this.  If so it would be a better question for the networking experts.

Roy


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Xilinx Employee
Xilinx Employee
876 Views
Registered: ‎11-29-2007

Re: [7 Series GTX] RXUSRCLK2, RXUSRCLK, and RXOUTCLK turned off abnormally

hello,

USRCLK are commonly driven by OUTCLK, so if the OUTCLK goes flat, also the USRCLK will be flat.

RX/TXPD is the GT powerdown. If you toggle it from normal operation (00) to longer recovery time (10) something will happen.

Please notice that PD might trigger a reset, and just after reset the OUTCLK could have holes for short time.

Additionally, after RXPD is deasserted, GTRXRESET must be toggled.

hope it helps

 

Observer prakashdrj
Observer
858 Views
Registered: ‎07-12-2016

Re: [7 Series GTX] RXUSRCLK2, RXUSRCLK, and RXOUTCLK turned off abnormally

Hello @gguasti and @roym

Understood, PD might be having some effect but I also have the same problem when [RX/TX]PD = 2'b00 (Not Changing) and just change RXELECIDLE = 1'b0 -> 1'b1 and RXUSERRDY = 1'b0 due to MMCM lock lost. If this is the case what else causing the issue?

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Xilinx Employee
Xilinx Employee
846 Views
Registered: ‎11-29-2007

Re: [7 Series GTX] RXUSRCLK2, RXUSRCLK, and RXOUTCLK turned off abnormally

hello

RXELECIDLE is an output port. When it goes HIGH this means that the input signal level is below a threshold.

If this happens, probably the signal is not available at receiver pins, thus the CDR cannot make its job of recovering clock and data, and probably the reset FSM detects errors and starts resetting the receiver periodically.

 

Observer prakashdrj
Observer
843 Views
Registered: ‎07-12-2016

Re: [7 Series GTX] RXUSRCLK2, RXUSRCLK, and RXOUTCLK turned off abnormally

@gguasti I am not seeing any RESET coming to _gt module when clock becomes off. For which reset FSM are you talking about?

 

If rx line is ELECIDLE then it will not have phase frequency adaption but rxoutclk must be there, I believe.

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