02-17-2020 03:32 PM
02-17-2020 04:15 PM
02-18-2020 04:43 AM
Hello Dan @danwwright
Thanks & regards
02-21-2020 08:07 AM
Thanks- that's good information. Yes we can certainly supply external clocks on the REFCLK pins to both the GTP banks we'll be using. My concern is that any one of the Artix-7's will be recieving data to its RX at a clock rate determined by that stream. But won't then the clock rate at which data streams out of the TX bank ultimately be determined by the clock presented to its external REFCLK pins? If those two clocks do not exactly match one another then that Artix-7 will eventually become the site of some data over/under flow.
Is this matching best accomplished by ensuring that the external clocks on the two banks remain synched to one another? Or instead is there some way of (internal to the Artix-7) take the clock recovere from its incomming data stream and then use THAT to fix the data rate of the outgoing stream?
02-21-2020 08:42 AM
Also if we do source a clock from the zynq what differential standard should we choose on its output pins if we want to feed those directly into the Artix-7 REFCLK pins?
02-21-2020 12:22 PM
02-25-2020 12:52 AM
>Also if we do source a clock from the zynq what differential standard should we choose on its output pins if we want to feed those directly into the Artix-7 REFCLK pins?
I would recommended to use LVDS for a transceiver REFCLK.
LVDS clock buffer device is also very common and relatively cheap.
03-09-2020 11:51 PM
Do you have any updates on this post ? Did you find any solution for your design ?
If you find @aforencich 's answer is useful, could you please kindly marked this thread as Solved , so other users can learn from your experience ?
Thanks & regards