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danwwright
Contributor
Contributor
1,397 Views
Registered: ‎10-12-2014

7 series GTP transceiver clocking question

Hi-

We are beginning a new design which will utilize the GTP transceivers (which we have never designed with before) from a Zynq 7015 to a chain of Artix-7's.  The Zynq will be transmit only and will send out a simple continuous Aurora 8b10b stream (number of lanes TBD) to the first Artix-7 in the chain. That Artix-7 receives the data on one of it's quads that will be receive only.  That Artix-7 will use the data but must also repeat exactly this same data to the next Artix-7 in the chain.  The Artix-7 repeats this data using a completely different quad on the other side of the chip.  So that quad will be transmit only.  After that the chain continues.  So the data flow looks like this:
 
Zynq 7015 -->  Artix-7 -->  Artix-7 -->  Artix-7 -->  ...
 
So naturally we hope to use a single clock driving the whole chain.   Since the receiving quad on the Artix-7 will be receive only is there any need for that quad to be provided with some external MGTREFCLKs?  Our hope is that the Artix-7 will rather recover a clock from the received Aurora 8b10b stream.  Then once that clock is recovered inside the Artix-7 we hope to have that clock then drive the transmit out of it's separate transmit only quad on the other side of the chip.  If we are indeed able to do this and maintain a single clock  for the entire chain then we perhaps we need not supply some external MGTREFCLKs on the Artix-7's transmit only quad either?
 
Now before we go off and do something so insanely optimistic as lay out some PCB's with no external clocks being supplied to any of the Artix-7's MGTREFCLKxx pins should this scheme work in principle?
 
Thanks,
Dan Wright
 
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7 Replies
aforencich
Explorer
Explorer
1,384 Views
Registered: ‎08-14-2013

Every transceiver instance, RX or TX, needs a proper clock connected to MGTREFCLK. This is because of how the transceiver clocking and CDRs work. The ref clock is multiplied up to half of the line rate with a PLL, then phase interpolators are used to generate the local receive clock, matched to the receive data. So every chip in your chain will need to have the MGTREFCLK pins driven on all GTP banks that you're using. It might be a good idea to figure out which set of GTP banks you can use so that you only need to drive one set of MGTREFCLK pins; it should be possible for some number of adjacent banks to share the reference clock.
karnanl
Xilinx Employee
Xilinx Employee
1,327 Views
Registered: ‎03-30-2016

Hello Dan @danwwright 

  1.  @aforencich  is correct that every transceiver needs a clean clock for REFCLK pin. (Please see https://www.xilinx.com/support/answers/44549.html ). Your current system proposal will not work.
  2. If you want to maintain a single clock for your entire board chain, I would recommend to use one clock source (from zynq board) , and forward this clock to the next Artix-7 board (You may also need to use jitter cleaner device, to clean your clock before connect it to Artix-7 GTP MGTREFCLK pin )

Thanks & regards
Leo


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danwwright
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Registered: ‎10-12-2014

Thanks- that's good information.  Yes we can certainly supply external clocks on the REFCLK pins to both the GTP banks we'll be using.  My concern is that any one of the Artix-7's will be recieving data to its RX at a clock rate determined by that stream.  But won't then the clock rate at which data streams out of the TX bank ultimately be determined by the clock presented to its external REFCLK pins?  If those two clocks do not exactly match one another then that Artix-7 will eventually become the site of some data over/under flow.

Is this matching best accomplished by ensuring that the external clocks on the two banks remain synched to one another?  Or instead is there some way of (internal to the Artix-7) take the clock recovere from its incomming data stream and then use THAT to fix the data rate of the outgoing stream?

 

 

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danwwright
Contributor
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Registered: ‎10-12-2014

Also if we do source a clock from the zynq what differential standard should we choose on its output pins if we want to feed those directly into the Artix-7 REFCLK pins?

 

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aforencich
Explorer
Explorer
1,210 Views
Registered: ‎08-14-2013

There are several methods for dealing with the problem of differing reference clock frequencies for high seed serial data transmission. 1. Common reference clock. Supply all transceivers from the same reference clock. If the PLLs all do what they are supposed to do, then all of the serializers will run at exactly the same frequency. 2. Separate reference clocks + transmit phase interpolator. In this case, you use a software or digital PLL to control the phase interpolators in the transmit side of the MGTs to lock the transmit rate to the receive rate. 3. Transmit idle symbols or similar control characters periodically that can be inserted/deleted as necessary due to differences in reference clock frequencies. This is used in protocols such as Ethernet, PCIe, etc.
karnanl
Xilinx Employee
Xilinx Employee
1,039 Views
Registered: ‎03-30-2016

Hello @danwwright 

I think @aforencich  already answered most of your questions.

>Also if we do source a clock from the zynq what differential standard should we choose on its output pins if we want to feed those directly into the Artix-7 REFCLK pins?

I would recommended to use LVDS for a transceiver REFCLK.
LVDS clock buffer device is also very common and relatively cheap.
REFCLK.png


Regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
811 Views
Registered: ‎03-30-2016

Hello @danwwright 

Do you have any updates on this post ? Did you find any solution for your design ?
If you find @aforencich 's  answer is useful, could you please kindly marked this thread as Solved , so other users can learn from your experience ?

Thanks & regards
Leo


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