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akshay_acharya
Observer
Observer
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Registered: ‎10-11-2018

7 series GTX transceiver DFE register value selection

Hello,

In 7 series  GTX transceiver, for CTLE equalization the boost settings can be varied by using RX_DFE_KL_CFG2 [31:0] register. But to change the DFE tap values there is no information given in UG476_7series_Transceiver_Guide. Can someone guide me how to set the appropriate DFE tap values?  

 Regards,

Akshay kumar

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borisq
Xilinx Employee
Xilinx Employee
863 Views
Registered: ‎08-07-2007

hi @akshay_acharya 

 

typically, tuning DFE taps are not recommanded.

what is the issue that you encounter? please share some lights about why you wanted to tune DFE taps.

 

Thanks,

Boris

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akshay_acharya
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Registered: ‎10-11-2018

Hello,

Because for line-rate more than 10gbps,the link won't be stable. The link will be fluctuating, if I set the CTLE in auto-adapting mode or if I change CTLE in fixed mode . So I cannot get the eye-diagram properly. Hence I am planning to change the DFE tap values, so that the link will be stable.

Regards,

Akshay kumar

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borisq
Xilinx Employee
Xilinx Employee
840 Views
Registered: ‎08-07-2007

hi @akshay_acharya 

 

I'm afraid tuning DFE Taps manually may not help.

what's the transmitter? 

can IBERT be used for testing? 

 

Thanks,

Boris

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akshay_acharya
Observer
Observer
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Registered: ‎10-11-2018

Hello,

yeah I am using IBERT at both transmitter and receiver. Any document regarding DFE will help

Regards,

Akshay kumar 

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gguasti
Xilinx Employee
Xilinx Employee
824 Views
Registered: ‎11-29-2007

hello,

As Boris suggested, in the lucky case you will find a combination of parameters that will give you "a more stable result", this will be valid for the particular board in the particular temperature and power, on your particular laboratory desk :-) and cannot be a solution for the final product.

This is the reson why we are a bit reluctant to hack the DFE.

I would rather try to investigate more on the reason of the unstability:

  • can it be a particular pattern? i.e. a long sequence of commas
  • can it be one of the DFE taps saturating? you can use the DMONITOR port to discover it
  • would the LPM mode be more suitable for your case? You should know the IL of your channel.
  • how is the line terminated? are you using decoupling capacitors? is the RX bias polarized or floating? Does it make any difference if you change the RX bias?
  • Tables 4-12, 4-13 and 4-14 should be used to tune the CTLE stage and transmitter. This would require a good knowledge of the channel IL
  • as last choice, can it be one of the stages that is more responsible of the "unstability"? you could try to hold or override the values as explained at page 187 of UG476
akshay_acharya
Observer
Observer
812 Views
Registered: ‎10-11-2018

Hello sir,

You had specified that we can monitor weather TAPs are saturating using DMONITOROUT[7:0]. Let's take we are monitoring DFETAP2 . and  DMONITOR_CFG value equal to default value. In ug476 it is given that

" RXDFETAP2 [5:0] = DMONITOROUT[5:0] 

6'd0 = 0
6'd63 = Full scale "

I am not understanding how this will tell weather DFETAP2 working or not. Can you please help me with this.

and I had already taken care of other points what you mentioned. 

Regards,

Akshay kumar

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gguasti
Xilinx Employee
Xilinx Employee
780 Views
Registered: ‎11-29-2007

hello Akshay

TAPx = 0 can be possible, but generally a saturated (Full scale) tap is not a wanted condition. 

If this happens, you might try to tune the far end TX pre-post de-emphasis and CTLE setup.

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