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Observer
Observer
248 Views
Registered: ‎09-29-2019

7K410T board and 7V690T board transmission have error codes

The 7K410T board and the 7V690T board are interconnected by MGT and fiber optic. The GTX and GTH transmission line rates are 6 Gbps, the reference clock is 150 MHz, and the input clocks of the two boards are homologous clocks.

When the GTX of the 7K410T receives data from the V7 board, it will occasionally display 0s that receive N user clock cycles. At the same time, when the 0 is fast receiving, the MGT receiving reset signal will be pulled high. Is it 7K410T board? MGT setup problem or clock issue?

In addition, when the 7K410T sends data to the V7 board, the data is transmitted in the form of a frame, and the BC code is inserted once every 32 data, and there are 20,000 data in one frame. After transmitting 50,000 frames, the V7 receiving end displays an error. After this error, after the V7 receives the BC code, the data can return to normal. Why is there a bit error? Is the K7 board problem? Or is it a V7 board problem? Or the choice of the clock on both sides?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

回复: 7K410T board and 7V690T board transmission have error codes

hi @zhaoyuhang 

 

our reset fsm will be continously checking the data_valid_in. if data_valid_in is low, the reset fsm will assert GTRXRESET to restart the rx initialization.

if you are using the user data instead of the frame gen data, you need to either tie data_valid_in to 1, or set DON’T_RESET_ON_DATA_ERROR_IN to 1. so that the fsm will not restart the rx reset process.

 

Thanks,

Boris

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