11-12-2019 06:31 PM - edited 11-12-2019 10:21 PM
I use 160tffg676,linerate 2.5 Gbps,tx and rx use cpll,reference clock 125mhz,external and internal data width 16bit, txusrclk 156.25mhz，it works fine when i use both rx and tx in a channel but after i unplugged the rx sma or i powerdown the rx, tx start to lost package, a break on oscillpscope, after i powerdown the rx, the txbuff halffull flag jump between 0 and 1, i thounght it was the buffer that goes wrong but after i bypass the buffer the promblem still exsit, i tried all the configure method the problem still there. It bothers me for like a month, i hope someone could give me some clue what is go wrong
11-14-2019 01:12 PM
Please attach your *.xci file so we can look at the setup. The half full flag isn't an error and toggling is normal. Kee the TX buffer enabled as that is more robust. I would suggest monitoring a lot of the TX signals like TXRESET, CPLLLOCK, TXOUTCLK, TXUSERCLK/2, TXRESETDONE, TXUSRRDDY, TXELECIDLE, TXINHIBIT. You can skip any of these signals that are tied to a 0 or 1. If there is an MMCM in the user clock loops monitor it's lock signal. Check your voltage supplies for any interruptions.
There are protocols that will automatically restart a link reset if the RX is lost. IF there is a dont reset on error flag in the design make sure it is set to 1.
11-18-2019 02:39 AM - edited 11-18-2019 03:00 AM
Reason I thought sth wrong with the buffstatus is before i turned off the rx, it kept 00.So i thought i might go wrong when buffer write or read those data.
I use a same 156.25mhz clock from mmcm for tx userclk and usrclk/2,the mmcm locked ,cplllock txresetdone all keeps high and i tied dont reset on data error in high already, and tied elecidle and txinhibit to 0.
I don't know what can i do to "check my voltage supplies for any interruptions"
And it seems i cannot upload my .xci file, it says not match