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Participant
Participant
571 Views
Registered: ‎01-24-2018

80-b SerDes

I am trying to implement a BCDR on a Kintex-7 FPGA following XAPP1083. The module of this application note takes as input a 80-bit deserialized data, and I wonder how can be done with the FPGA IO resources since, as far as I know, ISERDES are only up to 8b.

 

Thanks in advance for your support.

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Xilinx Employee
Xilinx Employee
518 Views
Registered: ‎10-19-2011

Hi @oli669 ,

XAPP1083 is meant to work with the GTX serial transceivers available in Kintex-7 and not with the ISERDES of the SelectIO.

The serial data stream is oversampled with 12.44Gbps. You will not achieve that with a SelectIO. With -3 speedgrade and FF packages the GTX can run at this speed and it then can give you a data width of 80 bit.

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Xilinx Employee
Xilinx Employee
474 Views
Registered: ‎08-07-2007

hi @oli669 

 

you can have a look at this.

https://china.xilinx.com/support/documentation/application_notes/xapp523-lvds-4x-asynchronous-oversampling.pdf

 

Thanks,

Boris

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Teacher
Teacher
459 Views
Registered: ‎07-09-2009

quick question . BCDR ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
437 Views
Registered: ‎11-29-2007

BCDR? good question:
BCDR stands for Burst mode Clock and Data Recovery

the CDR is the module present in the receiver that realizes the passage from serial domain (no relationship to the REFCLK phase) to the parallel domain (known phase relationship to the recovered clock). The CDR lock time is an unbounded statistical quantity and the BCDR trick makes the lock time bounded: the locked condition will be met in no more than xx clock cycles.
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