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Contributor
Contributor
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Registered: ‎03-07-2018

ALIGN primitive in 7series GTX as sata

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Hi!

I am using 7 series GTX as serial port for sata project.

In sata there is an ALIGN Primitive (comma word) for synchronization. The standard says: 

The phy layer (GTX) is free to consume received ALIGN primitives. Implementations where the Phy dose not consume received ALIGN primitives shall effectively drop received ALIGN primitives ...

so I wonder if GTX consumes the ALIGN or not and how to know that. I read the documentation but could not find the answer.

 

Thanks in advance.

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Xilinx Employee
Xilinx Employee
526 Views
Registered: ‎03-30-2016

Hello @ahmad.zaklouta 

>so if I use RX elastic buffer and enabled clock correction, I will not see ALIGN primitive on the output of GTX and I don't need to handle it in link layer?

No, that's not correct.

If you are using elastic buffer and enabled clock correction, GTX RX may remove or duplicate ALIGNp word when needed.

So,
if TX REFCLK is faster than RX REFCLK, GTX RX will remove ALIGNp word periodically.
if TX REFCLK is slower than RX REFCLK, GTX RX will duplicate ALIGNp word periodically.
GTX will do clock correction job (so your link module does not need to perform this task), but GTX RX may output ALIGNp word sometimes.


Regards
Leo

 

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Xilinx Employee
Xilinx Employee
561 Views
Registered: ‎03-30-2016

Hello @ahmad.zaklouta 

It depends on your GTX configuration.

SATA protocol use ALIGNp word ( which consist of 4 characters (K28.5/D10.2/D10.2/D27.3)) to perform a clock-correction. 

If you are using RX elastic buffer and enabled clock correction, GTX will consume (or duplicate) ALIGNp word when necessary.

 

Please set parameters on "CB and CC sequence" tab to match your system/protocol implementation.
Regards
Leo

GTX_CC.png
Contributor
Contributor
534 Views
Registered: ‎03-07-2018

Hi @karnanl 

thank you for your answer.

so if I use RX elastic buffer and enabled clock correction, I will not see ALIGN primitive on the output of GTX and I don't need to handle it in link layer?

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Xilinx Employee
Xilinx Employee
527 Views
Registered: ‎03-30-2016

Hello @ahmad.zaklouta 

>so if I use RX elastic buffer and enabled clock correction, I will not see ALIGN primitive on the output of GTX and I don't need to handle it in link layer?

No, that's not correct.

If you are using elastic buffer and enabled clock correction, GTX RX may remove or duplicate ALIGNp word when needed.

So,
if TX REFCLK is faster than RX REFCLK, GTX RX will remove ALIGNp word periodically.
if TX REFCLK is slower than RX REFCLK, GTX RX will duplicate ALIGNp word periodically.
GTX will do clock correction job (so your link module does not need to perform this task), but GTX RX may output ALIGNp word sometimes.


Regards
Leo

 

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