10-15-2018 11:10 PM
"It has been determined that the DisplayPort RX/TX Subsystems and Video PHY product cannot meet Xilinx production level criteria for 7 Series GTHE2 and GTP devices."
Essentially 7 Series devices with GTHE2 and GTPE2 are unsupported -> for further info consult the Product Guides, which state:
For HDCP: UltraScale/UltraScale+ supports up to 5.4 Gb/s,
Kintex-7/Virtex-7 (-1 speed grade
supports up to 2.7 Gb/s, -2/
-3 supports up to 5.4 Gb/s), and Artix-7 is not supported
Is there further info on exactly why HDCP is not supported on Artix-7.? Is that the only limitation (i.e. using DP without HDCP on Artix-7 is fine ?),
10-19-2018 04:10 AM
The video clock maximum frequency is 297 MHz across all transceiver types except GTPE2 which is maxed at 148.5 MHz. This means GTPE2 cannot support video formats with video clocks > 148.5 MHz. For example, it cannot support 4Kp 60Hz at 2 PPC because it requires 297 MHz video clock. 4Kp 60Hz can be supported at 4 PPC because the video clock it requires is only 184.5 MHz.
one more reason is this primitive are no more supported from Vivado 2017.1 version I believe and assume .
Please find the below image
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10-23-2018 08:18 PM - edited 10-24-2018 04:45 PM
Thanks for the info.
I am a bit confused / would like further clarification on a few things.
You have mentioned that the GTPE2 cannot support video clocks > 148.5 MHz. However the Displayport standard has no set 'video clock' - data is serialized on the wire at one of four set rates (LBR - 1.62 Gbps, HBR - 2.7 Gbps, HBR2 - 5.4Gbps, HBR3 - 8.1 Gbps), the rate is selected such that there is enough bandwidth to support the current video mode - any leftover bandwidth is taken up by header information or stuffing symbols.
Are you possibly thinking of the GTPE2 reference clock ? This clock is typically 1/40 the line rate - i.e. HBR2 is 5.4 Gbps which gives a 135 MHz reference clock.. so is the limit on the reference clock 148.5 MHz ?
10-24-2018 08:45 AM
yes your correct .
10-24-2018 07:52 PM
@csattarthanks for the info, however this still doesn't quite add up.
If the rate is limited to HBR2 (135 MHz reference clock), then I don't see why, on that fact alone, support for Artix-7 has been deprecated. The core specifies Displayport v1.2 - which has a maximum bandwidth of HBR2 (https://en.wikipedia.org/wiki/DisplayPort#Specifications), so it can support the maximum bandwidth of Displayport v1.2..
There must be something else that is unsupported.. would you mind having a closer look into my original snippet, r.e. HDCP being unsupported..?
Essentially, my application of the core does not require HDCP - and the maximum bandwidth I need to support is HBR2, so if those are the only limitations I should be able to use the core..
11-08-2018 10:20 AM
I need to work with higher experts on this issue , once I have updated from them I will update you asap.
11-08-2018 04:21 PM
When you contact the experts, could you also reference my other question: https://forums.xilinx.com/t5/Serial-Transceivers/GTP-Manual-Phase-alignment-TXPHINITDONE-never-asserts/td-p/907794
Specifically the section about bit errors.
11-15-2018 06:30 PM
I had discussion with the higher experts this is what they have delivered "IN Vivado GTPE2 primitives are not supported and in-case user is able to use on the Vivado with the meeting timing then he can use it with out using the GTP2 .
11-15-2018 06:33 PM
here is your query :
Essentially, my application of the core does not require HDCP - and the maximum bandwidth I need to support is HBR2, so if those are the only limitations I should be able to use the core.
if the tool support it , then we can use it .