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Voyager
Voyager
613 Views
Registered: ‎08-16-2018

AXI4 Stream between FPGAs

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I need to communicate some GB/s between FPGAs with the minimum overhead and protocol addition.

The basic idea is to connect an AXI4-Stream master to transceiver "X" and in the other FPGA have the reciprocal transceiver connected to an AXI4-Stream slave.

The question is, like in school maths, what the "X" is? In that case, the simplest, lowest area "X" able to handle, ideally serially, a few GB/s.

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Adventurer
Adventurer
595 Views
Registered: ‎05-23-2018

One of the easiest ways to get that to work properly is to use the very nice Aurora IP, which includes Clock correction, high bandwidth, high performance and reasonably low amount of logic used inside the FPGA.

If you don't have any MGTs available, you would need to do something similar on regular SelectIO, which is more error-prone to get to work at high speed.

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Adventurer
Adventurer
596 Views
Registered: ‎05-23-2018

One of the easiest ways to get that to work properly is to use the very nice Aurora IP, which includes Clock correction, high bandwidth, high performance and reasonably low amount of logic used inside the FPGA.

If you don't have any MGTs available, you would need to do something similar on regular SelectIO, which is more error-prone to get to work at high speed.

View solution in original post