UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Voyager
Voyager
397 Views
Registered: ‎08-16-2018

AXI4 Stream between FPGAs

Jump to solution

I need to communicate some GB/s between FPGAs with the minimum overhead and protocol addition.

The basic idea is to connect an AXI4-Stream master to transceiver "X" and in the other FPGA have the reciprocal transceiver connected to an AXI4-Stream slave.

The question is, like in school maths, what the "X" is? In that case, the simplest, lowest area "X" able to handle, ideally serially, a few GB/s.

0 Kudos
1 Solution

Accepted Solutions
Adventurer
Adventurer
379 Views
Registered: ‎05-23-2018

Re: AXI4 Stream between FPGAs

Jump to solution

One of the easiest ways to get that to work properly is to use the very nice Aurora IP, which includes Clock correction, high bandwidth, high performance and reasonably low amount of logic used inside the FPGA.

If you don't have any MGTs available, you would need to do something similar on regular SelectIO, which is more error-prone to get to work at high speed.

1 Reply
Adventurer
Adventurer
380 Views
Registered: ‎05-23-2018

Re: AXI4 Stream between FPGAs

Jump to solution

One of the easiest ways to get that to work properly is to use the very nice Aurora IP, which includes Clock correction, high bandwidth, high performance and reasonably low amount of logic used inside the FPGA.

If you don't have any MGTs available, you would need to do something similar on regular SelectIO, which is more error-prone to get to work at high speed.