10-03-2019 10:44 PM
I want to add PLL for my Artix 7 project. I know that I can use the Clock wizard for PLL.
But in this wizard it is asking the exact frequency of input clock. I know only the range of frequency which I willl received
from GTP Clock data recovery circuit. But the CDR output will vary time to time depanding on the input at GTP.
Pls let us know how can I implement the PLL in this senario when the Input clock frequency is not fixed?
10-03-2019 11:02 PM
10-04-2019 12:01 AM
As an aside,
The Giga Bit Trancevers, have thier own tightly integrated PLL's , which are not part of the standard PLL one instantiates in the FPGA.
What are you trying to do withtis PLL that locks to the GT links ?
Normaly , one would expect the interface to the GT''s to be asyncornous to the on FPGA clock,
part of the block in the GT's is the final fifo that is used for the cross clock domain .
10-11-2019 10:39 PM
the CDR can track incoming data. but the incoming data's clock should be fixed. if the incoming data's clock frequency is not fixed, the CDR cannot follow it automatically. you have to change the CDR settings on the fly and reset GT to make sure CDR can re-lock to the new frequency.