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Explorer
Explorer
451 Views
Registered: ‎11-19-2010

Any documentation on AXI peripheral IPs?

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Is there any user guide or document to go through to develop an AXI peripheral IP with the IP packager?

I'm fairly familiar with AXI and I can access the spec, what I'd like is something additional to the raw HDL files that Vivado creates.

not a blocker, but I just feel I'm reverse-engineering source code, which is not the ideal situation.

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Moderator
Moderator
344 Views
Registered: ‎11-09-2015

Hi @jcabel 

The templates are just including registers and the logic to read and write to it. You just need to create your own logic to connect to this register to read and write them from inside the IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
393 Views
Registered: ‎11-09-2015

HI @jcabel 

What exactly are you trying to do? The HDL from the IP packager is fairly basic just to get you started.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
374 Views
Registered: ‎11-19-2010

 

objective: develop an IP with an AXI peripheral. Maybe I'm old school, but I cannot (or not my favourite) work without a minimum of documentation.

Yes, the HDL created by the IP packager is basic, and so any guideline could be as well.

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Moderator
Moderator
345 Views
Registered: ‎11-09-2015

Hi @jcabel 

The templates are just including registers and the logic to read and write to it. You just need to create your own logic to connect to this register to read and write them from inside the IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post