Any documentation on AXI peripheral IPs?

[jcabel]

Is there any user guide or document to go through to develop an AXI peripheral IP with the IP packager?

I'm fairly familiar with AXI and I can access the spec, what I'd like is something additional to the raw HDL files that Vivado creates.

not a blocker, but I just feel I'm reverse-engineering source code, which is not the ideal situation.

[florentw]

HI @jcabel 

What exactly are you trying to do? The HDL from the IP packager is fairly basic just to get you started.

[jcabel]

objective: develop an IP with an AXI peripheral. Maybe I'm old school, but I cannot (or not my favourite) work without a minimum of documentation.

Yes, the HDL created by the IP packager is basic, and so any guideline could be as well.

[florentw · Accepted solution]

Hi @jcabel 

The templates are just including registers and the logic to read and write to it. You just need to create your own logic to connect to this register to read and write them from inside the IP