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garengllc2
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Registered: ‎09-18-2020

Any examples of JESD PHY DRP configuration?

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I am working with a 7-series GTX JESD PHY and I would like to be able to dynamically control it (I have it working fine under static configurations).  I am using a uBlaze for my AXI configurations.

I've started researching what needs to be done and it feels a little daunting.  I know that PG198 shows AXI-registers which includes the ones for DRP.  Then UG476 shows the DRP commands for GTX transceivers.  But I am just having trouble understanding the best way to handle them.  I just want to be able to configure the line rate and ref clock (and anything else that might need to be done under the hood that usually is handled by the IP configurator when you make those changes yourself).

Are there any examples out there that show some configuration changes that can be used as a starting point?

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roym
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Registered: ‎07-30-2007

Xilinx application notes 746 and 1198 will include a microblaze design that controls the DRP port.

 

https://www.xilinx.com/support/documentation/application_notes/xapp1198-eye-scan.pdf




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roym
Moderator
Moderator
304 Views
Registered: ‎07-30-2007

Xilinx application notes 746 and 1198 will include a microblaze design that controls the DRP port.

 

https://www.xilinx.com/support/documentation/application_notes/xapp1198-eye-scan.pdf




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Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
----------------------------------------------------------------------------


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