cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
361 Views
Registered: ‎05-11-2018

Artix 7 GTP drive strength capability

Where can I find the drive capability of the Artix 7 GTPs?  We would like to consider using one set of FPGA transceivers (4 data and 1 clock) to drive 3 separate LVDS receiver interfaces on 3 separate ASICs.  Can this be done?

Kerry

0 Kudos
3 Replies
Highlighted
Teacher
Teacher
349 Views
Registered: ‎07-09-2009

Re: Artix 7 GTP drive strength capability

Why do you think the GTP pins are LVDS ? I think its only the clock inputs on the GTx are LVDS.

this might help

https://forums.xilinx.com/t5/Welcome-Join/LVDS-on-Transceiver-pins/td-p/671414

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Contributor
Contributor
343 Views
Registered: ‎05-11-2018

Re: Artix 7 GTP drive strength capability

We already have a working interface to drive an ASIC LVDS interface.  We now want to expand to driving 3 ASICs instead of just one and would like to avoid the need of a larger package FPGA with more LVDS transceiver banks to drive them separately.  So I need to know if each of the tranceivers has enough drive strength to drive 3 loads.

0 Kudos
Highlighted
Teacher
Teacher
287 Views
Registered: ‎07-09-2009

Re: Artix 7 GTP drive strength capability

If its for production, I'd say your running on your own,
GTx are designed for point to point, and I'd guess only tested like that.
OK the largest load is going to be the single external termination resistor, but the AC loading is going to be horrendous,

Are you going to AC couple all the ASIC inputs separately, so your going to have a bunch of capacitors in parallel, if you dont then the ASIC bias in each chip is going to fight.

Id say your best bet it to try simulating , Xilinx have the models for the GTx pins, see what that does,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos