08-16-2019 12:18 PM
Where can I find the drive capability of the Artix 7 GTPs? We would like to consider using one set of FPGA transceivers (4 data and 1 clock) to drive 3 separate LVDS receiver interfaces on 3 separate ASICs. Can this be done?
08-16-2019 12:35 PM
08-16-2019 12:47 PM
We already have a working interface to drive an ASIC LVDS interface. We now want to expand to driving 3 ASICs instead of just one and would like to avoid the need of a larger package FPGA with more LVDS transceiver banks to drive them separately. So I need to know if each of the tranceivers has enough drive strength to drive 3 loads.
08-17-2019 04:33 AM