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Visitor
Visitor
373 Views
Registered: ‎01-08-2020

Artix 7 GTP

Looking at U482 7 Series GTP Transceiver datasheet (page 235) it indicates that certain pins in Bank 16 and bank 35 are "prohibited" from use if you use GTPs.  The Xilinx Advisory 58162 indicates that the issue is with the wirebond and potentially crosstalk of the wires from logic to pin. 

I am looking for clarification on these statements.  Bank 16 and 35 are mechanically located near the GTP bank 216 and NOT bank 213. So I can understand the limit to pins used in those banks.  I cannot understand the limitation if only 213 is used. 

Are the pins in Bank 16 and 35 prohibited if Bank 216 is NOT used?   

Any insight is appreciated.

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Moderator
Moderator
343 Views
Registered: ‎07-30-2007

I suspect this is more SSN than crosstalk which would be more associated with the power planes than the proximity of the wires.  I don't actually see any mention of crosstalk in the advisory.  Where did you see that?  Are you intending to use the FGG676 at greater than 6 Gbps?




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Teacher
Teacher
336 Views
Registered: ‎07-09-2009

I would take this from what you have read.

The FFG1156 is a terrible package for Power supply bouncing, the wires in the package from the "pins" to the "silicon" are "long"

Its a cheap package, and you are going to have to expect compramises.

MGTs are working "hard" when your at the multi Gb/s rate, and again the FFG1156 package is not great for these signals. You have to expect limitations with this package,

If you want to run the MGTs ,and your experience in these sort of speeds and things is low, IMHO, I'd suggest that the FFG1156 is not for you.


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Visitor
Visitor
273 Views
Registered: ‎01-08-2020

Crosstalk was a deduction based on the information in the advisory (indications of the wirebond, performance, speed, and pins in the area of Bank 216 only, not 213).  Possibly an incorrect assumption. 

The intent is use only bank 213 at 6Gpbs (ESATA) not Bank 216.   The banks around the 213 and 216 would be down around 100-150MHz with external clocking being 40-50MHZ. 

I noticed in other advisories for the rest of the 7 series that most references were to power issues as you indicate.  The other advisories indicated that only a certain number of I/O could be used in certain columns.  They did not prohibit the use of a specific pin. 

 

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Visitor
Visitor
272 Views
Registered: ‎01-08-2020

Is the FFG1156 similar to the FGG676 package mentioned in the Advisory? 

Are you inferring that the advisory conclusion is based on power and not on other factors?

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Moderator
Moderator
247 Views
Registered: ‎07-30-2007

An FFG part is not actually wire bonded so it is not part of this.  Wire bonded packages are more susceptible to SSO and it looks like that is this issue with this advisory. 




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